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參數(shù)資料
| 型號(hào)： | CY62256LL-70SNC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 256K (32K x 8) Static RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 70 ns, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 394K |
| 代理商： | CY62256LL-70SNC |
CY62256
Document #: 38-05248 Rev. *C
Page 6 of 12
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
SUPPLY
CURRENT
Read Cycle No. 2
[13, 14]
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
CE
WE
OE
t
HZOE
DATA
IN
VALID
NOTE
Write Cycle No. 1 (WE Controlled)
[10, 15, 16]
17
t
WC
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE
WE
DATA I/O
ADDRESS
CE
DATA
IN
VALID
Write Cycle No. 2 (CE Controlled)
[10, 15, 16]
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PDF描述 |
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| CY62256LL-70SNI | 256K (32K x 8) Static RAM |
| CY62256LL-70ZC | 256K (32K x 8) Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62256LL-70SNC.DS | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 70ns 28-Pin SNC N |
| CY62256LL-70SNCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 70ns 28-Pin SNC N T/R |
| CY62256LL-70SNCX | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 70ns 28-Pin SNC N |
| CY62256LL-70SNI | 制造商:Rochester Electronics LLC 功能描述:256K (32K X 8)- SLOW ASYNCH SRAM - Bulk |
| CY62256LL-70SNIT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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