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參數(shù)資料
| 型號(hào)： | CY7C028V-20ACT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 3.3V 32K/64K x 16/18 Dual-Port Static RAM |
| 中文描述： | 64K X 16 DUAL-PORT SRAM, 20 ns, PQFP100 |
| 封裝： | PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 22/22頁 |
| 文件大小： | 635K |
| 代理商： | CY7C028V-20ACT |
CY7C027V/027AV/028V
CY7C037AV/038V
Document #: 38-06078 Rev. *D
Page 9 of 22
Data Retention Mode
The CY7C027V/027AV/028V and CY7037AV/038V are de-
signed with battery backup in mind. Data retention voltage and
supply current are guaranteed over temperature. The following
rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention, within
VCC to VCC – 0.2 V
2. CE must be kept between VCC – 0.2 V and 70% of VCC during
the power up and power down transitions
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0 V)
tHD
Data hold from write end
0
–
0
–
0
–
ns
tHZWE[17, 18]
R/W LOW to High Z
–
10
–
12
–
15
ns
tLZWE[17, 18]
R/W HIGH to Low Z
3
–
3
–
3
–
ns
tWDD[21]
Write pulse to data delay
–
30
–
40
–
50
ns
tDDD[21]
Write data valid to read data valid
–
25
–
30
–
35
ns
Busy Timing[19]
tBLA
BUSY LOW from address match
–
15
–
20
–
20
ns
tBHA
BUSY HIGH from address mismatch
–
15
–
20
–
20
ns
tBLC
BUSY LOW from CE LOW
–
15
–20–20
ns
tBHC
BUSY HIGH from CE HIGH
–15
–
16–17
ns
tPS
Port setup for priority
5
–
5
–
5
–
ns
tWB
R/W HIGH after BUSY (Slave)
0
–0
–
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
13–15–17–
ns
tBDD[21]
BUSY HIGH to data valid
–
15
–
20
–
25
ns
Interrupt Timing[19]
tINS
INT set time
–
15
–
20
–
20
ns
tINR
INT reset time
–
15
–
20
–
20
ns
Semaphore Timing
tSOP
SEM flag update pulse (OE or SEM)
10–10–12–
ns
tSWRD
SEM flag write to read time
5
–
5
–
5
–
ns
tSPS
SEM flag contention window
5
–
5
–
5
–
ns
tSAA
SEM address access time
–
15
–
20
–
25
ns
Switching Characteristics Over the Operating Range[12](continued)
Parameter
Description
CY7C027V/027AV/028V/
CY7C037AV/CY7C038V
Unit
-15
-20
-25
Min
Max
Min
Max
Min
Max
Timing
Parameter
Test Conditions[22]
Max
Unit
ICCDR1
At VCCDR = 2 V
50
A
Data Retention Mode
3.0 V
VCC 2.0 V
VCC to VCC – 0.2 V
VCC
CE
tRC
V
IH
Notes
17. Test conditions used are Load 2
18. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer
to Figure 11.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 waveform.
20. Test conditions used are Load 1.
21. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
22. CE = VCC, Vin = GND to VCC, TA = 25 C. This parameter is guaranteed but not tested.
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