參數(shù)資料
型號: CY7C0852AV-133AXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
中文描述: 128K X 36 DUAL-PORT SRAM, 4 ns, PQFP176
封裝: 24 X 24 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-176
文件頁數(shù): 28/36頁
文件大小: 956K
代理商: CY7C0852AV-133AXI
CY7C0850AV,CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document #: 38-06070 Rev. *J
Page 34 of 36
Document History Page
Document Title: CY7C0850AV, CY7C0851V/CY7C0851AV, CY7C0852V/CY7C0852AV, CY7C0853V/CY7C0853AV,
FLEx36 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
Document Number: 38-06070
REV.
ECN NO.
Submis-
sion Date
Orig. of
Change
Description of Change
**
127809
08/04/03
SPN
This data sheet has been extracted from another data sheet: the 2M/4M/9M
data sheet. The following changes have been made from the original as
pertains to this device:
Updated capacitance values
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Corrected 0853 pins L3 and L12
Added discussion of Pause/Restart for JTAG boundary scan
Power up requirements added to Maximum Ratings information
Revise tcd2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns
Updated Icc numbers
Updated tHA, tHB, tHD for -100 speed
Separated out from the 4M data sheet
Added 133-MHz Industrial device to Ordering Information table
*A
210948
See ECN
YDT
Changed mailbox addresses from 1FFFE and 1FFFF to 3FFFE and 3FFFF.
*B
216190
See ECN
YDT/Dcon Corrected Revision of Document. CMS does not reflect this rev change
*C
231996
See ECN
YDT
Removed “A particular port can write to a certain location while another port is
reading that location.” from Functional Description.
*D
238938
See ECN
WWZ
Merged 0853 (9Mx36) with 0852 (4Mx36) and 0851(2Mx36), add 0850 (1M x36),
to the data sheet.
Added product selection table.
Added JTAG ID code for 1M device.
Added note 14.
Updated boundary scan section.
Updated function description for the merge and addition.
*E
329122
See ECN
SPN
Updated Marketing part numbers
*F
389877
See ECN
KGH
Updated Read-to-Write-to-Read timing diagram to reflect accurate bus
turnaround scheme.
Added ISB5
Changed tRSCNTINT to 10ns
Changed tRSF to 10ns
Added figure Disabled-to-Read-to-Read-to-Read-to-Write
Added figure Disabled-to-Write-to-Read-to-Write-to-Read
Added figure Disabled-to-Read-to-Disabled-to-Write
Added figure Read-to-Readback-to-Read-to-Read (R/W = HIGH)
Updated Read-to-Write-to-Read timing diagram to correct the data out schemes
Updated Disabled-to-Read-to-Read-to-Read-to-Write timing diagram to correct
the chip enable, data in, and data out schemes
Updated Disabled-to-Write-to-Read-to-Write-to-Read timing diagram to correct
the chip enable and output enable schemes
Updated Disabled-to-Read-to-Disabled-to-Write timing diagram to correct the
chip enable and output enable schemes
*G
391597
See ECN
SPN
Updated counter reset section to reflect mirror register behavior
*H
2544945
07/29/08
VKN/AESA Updated Template. Updated ordering information
*I
2897087
03/22/10
RAME
Removed obsolete parts from ordering information table
Updated package diagrams
相關(guān)PDF資料
PDF描述
CY7C0852AV-133BBI FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0852AV-167AXC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853AV-100BBC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853AV-100BBI FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0853AV-133BBC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
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CY7C0852AV-133BBCT 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 128KX36 4.7NS 172FBGA - Tape and Reel
CY7C0852AV-133BBI 功能描述:靜態(tài)隨機(jī)存取存儲器 4MB (128Kx36) 3.3v 133MHz Synch 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C0852AV-167AC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 128KX36 4NS 176TQFP - Trays
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