參數(shù)資料
型號(hào): CY7C0852AV-167AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
中文描述: 128K X 36 DUAL-PORT SRAM, 4 ns, PQFP176
封裝: 24 X 24 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-176
文件頁數(shù): 7/36頁
文件大?。?/td> 956K
代理商: CY7C0852AV-167AXC
CY7C0850AV,CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document #: 38-06070 Rev. *J
Page 15 of 36
Figure 6. AC Test Load and Waveforms
Switching Characteristics
Over the Operating Range
Parameter
Description
-167
-133
-100
Unit
CY7C0850AV
CY7C0851V/AV
CY7C0852V/AV
CY7C0850AV
CY7C0851V/AV
CY7C0852V/AV
CY7C0853V
CY7C0853AV
CY7C0853V
CY7C0853AV
Min
Max
Min
Max
Min
Max
Min
Max
fMAX2
Maximum operating frequency
167
133
133
100
MHz
tCYC2
Clock cycle time
6.0
7.5
7.5
10.0
ns
tCH2
Clock HIGH time
2.7–3.0
3.0–
4.0–
ns
tCL2
Clock LOW time
2.7
3.0
3.0
4.0
ns
Clock rise time
2.0
2.0
2.0
3.0
ns
Clock fall time
2.0
2.0
2.0
3.0
ns
tSA
Address setuptime
2.3
2.5
2.5
3.0
ns
tHA
Address hold time
0.6
0.6
0.6
0.6
ns
tSB
Byte select setup time
2.3
2.5
2.5
3.0
ns
tHB
Byte select hold time
0.6
0.6
0.6
0.6
ns
tSC
Chip enable setup time
2.3
2.5
NA
NA
ns
tHC
Chip enable hold time
0.6
0.6
NA
NA
ns
tSW
R/W setup time
2.3
2.5
2.5
3.0
ns
tHW
R/W hold time
0.6
0.6
0.6
0.6
ns
tSD
Input data setup time
2.3
2.5
2.5
3.0
ns
tHD
Input data hold time
0.6
0.6
0.6
0.6
ns
tSAD
ADS setup time
2.3
2.5
NA
NA
ns
tHAD
ADS hold time
0.6
0.6
NA
NA
ns
tSCN
CNTEN setup time
2.3
2.5
NA
NA
ns
tHCN
CNTEN hold time
0.6
0.6
NA
NA
ns
tSRST
CNTRST setup time
2.3
2.5
NA
NA
ns
tHRST
CNTRST hold time
0.6
0.6
NA
NA
ns
tSCM
CNT/MSK setup time
2.3
2.5
NA
NA
ns
tHCM
CNT/MSK hold time
0.6
0.6
NA
NA
ns
R1 = 590
R2 = 435
C = 5 pF
(b) Three-state Delay (Load 2)
90%
10%
3.0 V
VSS
90%
10%
<2 ns
ALL INPUT PULSES
3.3 V
VTH = 1.5 V
R = 50
Z0 = 50
(a) Normal Load (Load 1)
C = 10 pF
OUTPUT
Note
23. Except JTAG signals (tr and tf < 10 ns [max.]).
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