參數(shù)資料
型號: CY7C0853AV-133BBC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
中文描述: 256K X 36 DUAL-PORT SRAM, 4.7 ns, PBGA172
封裝: 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, FBGA-172
文件頁數(shù): 18/36頁
文件大小: 956K
代理商: CY7C0853AV-133BBC
CY7C0850AV,CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document #: 38-06070 Rev. *J
Page 25 of 36
Figure 20. Readback State of Address Counter or Mask Register[45, 46, 47, 48]
Switching Waveforms (continued)
CNTEN
CLK
tCH2
tCL2
tCYC2
ADDRESS
ADS
An
Qx-2
Qx-1
Qn
tSA tHA
tSAD tHAD
tSCN tHCN
LOAD
ADDRESS
EXTERNAL
tCD2
INTERNAL
ADDRESS
An+1
An+2
An
tCKHZ
DATAOUT
An*
Qn+3
Qn+1
Qn+2
An+3
An+4
tCKLZ
tCA2 or tCM2
READBACK
INTERNAL
COUNTER
ADDRESS
INCREMENT
EXTERNAL
A0–A16
Notes
45. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
46. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.
47. Address in input mode. Host can drive address bus after tCKHZ.
48. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
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