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參數(shù)資料
| 型號(hào)： | CY7C1011CV33-15ZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K x 16 Static RAM |
| 中文描述： | 128K X 16 STANDARD SRAM, 15 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 284K |
| 代理商： | CY7C1011CV33-15ZI |
CY7C1011CV33
Document #: 38-05232 Rev. *C
Page 4 of 11
AC Test Loads and Waveforms[3]
AC Switching Characteristics Over the Operating Range [4]
Parameter
Description
-10
-12
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tpower
[5]
VCC(typical) to the first access
1
s
tRC
Read Cycle Time
10
12
15
ns
tAA
Address to Data Valid
10
12
15
ns
tOHA
Data Hold from Address Change
3
ns
tACE
CE LOW to Data Valid
10
12
15
ns
tDOE
OE LOW to Data Valid
5
6
7
ns
tLZOE
OE LOW to Low-Z
0
ns
tHZOE
OE HIGH to High-Z[6, 7]
56
7
ns
tLZCE
CE LOW to Low-Z[7]
333
ns
tHZCE
CE HIGH to High-Z[6, 7]
56
7
ns
tPU
CE LOW to Power-up
0
ns
tPD
CE HIGH to Power-down
10
12
15
ns
tDBE
Byte Enable to Data Valid
5
6
7
ns
tLZBE
Byte Enable to Low-Z
0
ns
tHZBE
Byte Disable to High-Z
6
7
ns
Write Cycle[8, 9]
tWC
Write Cycle Time
10
12
15
ns
Notes:
3. AC characteristics (except High-Z) for all 10-ns parts are tested using the load conditions shown in (a). All other speeds are tested using the Thevenin load shown
in (b). High-Z characteristics are tested for all speeds using the test load shown in (d).
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
(b)
R 317
R2
351
Rise Time: 1 V/ns
Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50
50
1.5V
(c)
(a)
3.3V
OUTPUT
5 pF
(d)
R 317
R2
351
10-ns devices:
12-, 15-ns devices:
High-Z characteristics:
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1011CV33-15ZXC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 2M-Bit 128K x 16 15ns 44-Pin TSOP-II |
| CY7C1011DV33-10BVI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M FAST ASYNC HI SPD 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1011DV33-10BVIKA | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1011DV33-10BVIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M FAST ASYNC HI SPD 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1011DV33-10BVXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M FAST ASYNC HI SPD 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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