參數(shù)資料
型號(hào)： CY7C1061AV33-8BAI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 1M x 16 Static RAM
中文描述： 1M X 16 STANDARD SRAM, 8 ns, PBGA48
封裝： 8 X 20 MM, 1.20 MM HEIGHT, MINI, FBGA-48
文件頁(yè)數(shù)： 4/11頁(yè)
文件大?。?/td> 269K
代理商： CY7C1061AV33-8BAI
PRELIMINARY
CY7C1061AV25
Document #: 38-05331 Rev. **
Page 4 of 11
AC Test Loads and Waveforms
[3]
AC Switching Characteristics
Over the Operating Range
[4]
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[8, 9]
t
WC
t
SCE
Notes:
3.
Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
(2.3V). As soon as 1ms (T
power
) after reaching the
minimum operating V
, normal SRAM operation can begin including reduction in V
to the data retention (V
, 1.5V) voltage.
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.5V, and output loading of the specified
I
/I
and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
5.
This part has a voltage regulator which steps down the voltage from 2.5V to 2V internally. t
power
time has to be provided initially before a Read/Write operation
is started.
6.
t
, t
, t
, t
HZBE
and t
LZOE
, t
LZCE
, t
\LZWE
, t
LZBE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±
200 mV from
steady-state voltage.
7.
These parameters are guaranteed by design and are not tested.
8.
The internal Write time of the memory is defined by the overlap of CE
LOW (CE
HIGH) and WE LOW. Chip enables must be active and WE and byte enables must
be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of
the signal that terminates the Write.
9.
The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Description
-8
-10
-12
Unit
Min.
Max.
Min.
Max.
Min.
Max.
V
CC
(typical) to the first access
[5]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW/CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
[6]
CE
1
LOW/CE
2
HIGH to Low-Z
[6]
CE
1
HIGH/CE
2
LOW to High-Z
[6]
CE
1
LOW/CE
2
HIGH to Power-up
[7]
CE
1
HIGH/CE
2
LOW to Power-down
[7]
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
1
8
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
12
8
10
12
3
3
3
8
5
10
5
12
6
1
1
1
5
5
6
3
3
3
5
5
6
0
0
0
8
5
10
5
12
6
1
1
1
5
5
6
Write Cycle Time
CE
1
LOW / CE
2
HIGH to Write End
8
6
10
7
12
8
ns
ns
90%
10%
2.5V
GND
90%
10%
ALL INPUT PULSES
2.5V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE
(a)
(b)
R1 1667
R2
1538
Rise time > 1V/ns
Fall time:
> 1V/ns
(c)
OUTPUT
50
Z
0
= 50
V
TH
= V
DD
/2
30 pF*
* Capacitive Load consists of all com-
ponents of the test environment.
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