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參數(shù)資料
| 型號： | CY7C1061BV33-12ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 16-Mbit (1M x 16) Static RAM |
| 中文描述： | 1M X 16 STANDARD SRAM, 12 ns, PDSO54 |
| 封裝： | TSOP2-54 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 301K |
| 代理商： | CY7C1061BV33-12ZC |
16-Mbit (1M x 16) Static RAM
CY7C1061BV33
Cypress Semiconductor Corporation
Document #: 38-05693 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 3, 2006
Features
High speed
— t
AA
= 10 ns
Low active power
— 990 mW (max.)
Operating voltages of 3.3 ± 0.3V
2.0V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Available in Pb-free and non Pb-free 54-pin TSOP II
package
Functional Description
The CY7C1061BV33 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
Writing to the device is accomplished by enabling the chip (CE
LOW) while forcing the Write Enable (WE) input LOW. If Byte
Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
19
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
19
).
Reading from the device is accomplished by enabling the chip
by taking CE LOW while forcing the Output Enable (OE) LOW
and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O
0
to I/O
7
. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O
8
to
I/O
15
. See the truth table at the back of this data sheet for a
complete description of Read and Write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW and WE LOW).
The CY7C1061BV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
1
A
1
A
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
R
S
INPUT BUFFER
1M x 16
ARRAY
A
0
A
1
A
1
A
1
A
1
A
1
A
1
A
1
I/O
0
–I/O
7
OE
BLE
I/O
8
–I/O
15
CE
WE
BHE
A
1
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
41
43
42
16
17
29
28
A
5
A
6
A
7
A
8
A
9
NC
A
0
A
1
OE
V
SS
DNU/V
SS
V
SS
I/O
15
A
17
A
16
A
15
A
2
CE
V
CC
I/O
2
V
SS
I/O
0
V
CC
I/O
1
BHE
A
3
A
4
18
19
20
21
I/O
3
27
25
26
22
23
24
I/O
6
I/O
5
V
CC
I/O
4
I/O
7
V
SS
BLE
A
10
V
CC
I/O
13
I/O
14
I/O
12
I/O
10
I/O
9
V
CC
I/O
8
A
14
A
13
A
12
A
11
44
46
45
47
50
49
48
51
53
52
54
A
19
A
18
I/O
11
V
SS
DNU/V
CC
54-pin TSOP II (Top View)
Notes:
1. DNU/V
Pin (#16) has to be left floating or connected to V
CC
and DNU/V
SS
Pin (#40) has to be left floating or connected to V
SS
to ensure proper application.
2. NC – No Connect Pins are not connected to the die
PinConfigurations
[1, 2]
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| CY7C1061BV33-8ZC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 16M-Bit 1M x 16 8ns 54-Pin TSOP-II 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3.3V 16MBIT 1MX16 8NS 54TSOP-II - Bulk 制造商:Rochester Electronics LLC 功能描述:16MB- (1MX16) FAST ASYNCH SRAM 3.3V TSOP II 54 - Bulk |
| CY7C1061BV33-8ZXC | 制造商:Cypress Semiconductor 功能描述:1M x 16 CPG Fast Async SRAM 制造商:Cypress Semiconductor 功能描述:16MB- (1MX16) FAST ASYNCH SRAM 3.3V TSOP II 54 - Bulk |
| CY7C1061BV33-8ZXCT | 制造商:Cypress Semiconductor 功能描述:16MB- (1MX16) FAST ASYNCH SRAM 3.3V TSOP II 54 - Tape and Reel |
| CY7C1061BV33-8ZXI | 功能描述:IC SRAM 16MBIT 8NS 54TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
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