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參數(shù)資料
| 型號： | CY7C1061BV33-12ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 16-Mbit (1M x 16) Static RAM |
| 中文描述： | 1M X 16 STANDARD SRAM, 12 ns, PDSO54 |
| 封裝： | TSOP2-54 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 301K |
| 代理商： | CY7C1061BV33-12ZC |
CY7C1061BV33
Document #: 38-05693 Rev. *B
Page 3 of 9
AC Test Loads and Waveforms
[5]
AC Switching Characteristics
Over the Operating Range
[6]
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Notes:
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
(3.0V). As soon as 1ms (T
power
) after reaching the
minimum operating V
, normal SRAM operation can begin including reduction in V
to the data retention (V
, 2.0V) voltage.
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
7. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
power
time has to be provided initially before a Read/Write operation is
started.
8. t
, t
HZCE
, t
HZWE
, t
HZBE
and t
LZOE
, t
LZCE
, t
\LZWE
, t
LZBE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±
200 mV from steady-state
voltage.
9. These parameters are guaranteed by design and are not tested.
10.The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Chip enables must be active and WE and byte enables must be LOW to
initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Description
–10
–12
Unit
Min.
Max.
Min.
Max.
V
CC
(typical) to the first access
[7]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
[8]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[8]
CE LOW to Power-Up
[9]
CE HIGH to Power-Down
[9]
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
12
10
12
3
3
10
5
12
6
1
1
5
6
3
3
5
6
0
0
10
5
12
6
1
1
5
6
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE
(a)
(b)
R1 317
R2
351
Rise time > 1V/ns
Fall time: > 1V/ns
(c)
OUTPUT
50
Z
0
= 50
V
TH
= 1.5V
30 pF*
* Capacitive Load consists of all com-
ponents of the test environment.
[+] Feedback
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| CY7C1061BV33-8ZC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 16M-Bit 1M x 16 8ns 54-Pin TSOP-II 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3.3V 16MBIT 1MX16 8NS 54TSOP-II - Bulk 制造商:Rochester Electronics LLC 功能描述:16MB- (1MX16) FAST ASYNCH SRAM 3.3V TSOP II 54 - Bulk |
| CY7C1061BV33-8ZXC | 制造商:Cypress Semiconductor 功能描述:1M x 16 CPG Fast Async SRAM 制造商:Cypress Semiconductor 功能描述:16MB- (1MX16) FAST ASYNCH SRAM 3.3V TSOP II 54 - Bulk |
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| CY7C1061BV33-8ZXI | 功能描述:IC SRAM 16MBIT 8NS 54TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C1061BV33-8ZXIT | 制造商:Cypress Semiconductor 功能描述:16MB- (1MX16) FAST ASYNCH SRAM 3.3V TSOP II 54 - Tape and Reel |
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