參數(shù)資料
型號: CY7C1062AV33-12BGC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 512K x 32 Static RAM
中文描述: 512K X 32 STANDARD SRAM, 12 ns, PBGA119
封裝: 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
文件頁數(shù): 4/9頁
文件大小: 311K
代理商: CY7C1062AV33-12BGC
CY7C1062AV33
Document #: 38-05137 Rev. *F
Page 4 of 9
AC Switching Characteristics
Over the Operating Range
[6]
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Description
–8
–10
–12
Unit
Min.
Max.
Min.
Max.
Min.
Max.
V
CC
(typical) to the first access
[7]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
, CE
2
,
or CE
3
LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8]
CE
1
, CE
2
,
or CE
3
LOW to Low-Z
[8]
CE
1
, CE
2
,
or CE
3
HIGH to High-Z
[8]
CE
1
, CE
2
,
or CE
3
LOW to Power-up
[9]
CE
1
, CE
2
,
or CE
3
HIGH to Power-down
[9]
Byte Enable to Data Valid
Byte Enable to Low-Z
[8]
Byte Disable to High-Z
[8]
1
8
1
10
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
8
10
12
3
3
3
8
5
10
5
12
6
1
1
1
5
5
6
3
3
3
5
5
6
0
0
0
8
5
10
5
12
6
1
1
1
5
5
6
Write Cycle Time
CE
1
, CE
2
, or CE
3
LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[8]
WE LOW to High-Z
[8]
Byte Enable to End of Write
8
6
6
0
0
6
5
0
3
10
7
7
0
0
7
5.5
0
3
12
8
8
0
0
8
6
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
6
6
7
8
Data Retention Waveform
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and transmission line loads. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise.
7. This part has a voltage regulator that steps down the voltage from 3V to 2V internally. t
time has to be provided initially before a read/write operation is started.
8. t
, t
, t
, t
, and t
, t
LZCE
, t
LZWE
, and t
LZBE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
± 200 mV from steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10.The internal write time of the memory is defined by the overlap of CE
LOW, CE
HIGH, CE
LOW, and WE LOW. The chip enables must be active and WE
must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to
the leading edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
3.0V
3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
[+] Feedback
相關(guān)PDF資料
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CY7C1062AV33-12BGI The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits.
CY7C1062AV33-8BGC The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits.
CY7C1062AV33-8BGI The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits.
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