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參數資料
| 型號： | CY7C1062AV33-10BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits. |
| 中文描述： | 512K X 32 STANDARD SRAM, 10 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁數： | 1/9頁 |
| 文件大?。?/td> | 188K |
| 代理商： | CY7C1062AV33-10BGC |
512K x 32 Static RAM
CY7C1062AV33
Cypress Semiconductor Corporation
Document #: 38-05137 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised February 21, 2003
Features
High speed
—t
AA
= 8, 10, 12 ns
Low active power
—1080 mW (max.)
Operating voltages of 3.3 ± 0.3V
2.0V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and CE
3
features
Functional Description
The CY7C1062AV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 32 bits.
Writing to the device is accomplished by enabling the chip
(CE
1,
CE
2
and CE
3
LOW) and forcing the Write Enable (WE)
input LOW. If Byte Enable A (B
A
) is LOW, then data from I/O
pins (I/O
0
through I/O
7
), is written into the location specified on
the address pins (A
0
through A
18
). If Byte Enable B (B
B
) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
18
).
Likewise, B
C
and B
D
correspond with the I/O pins I/O
16
to I/O
23
and I/O
24
to I/O
31
, respectively.
Reading from the device is accomplished by enabling the chip
(CE
1,
CE
2
,
and CE
3
LOW) while forcing the Output Enable
(OE) LOW and Write Enable (WE) HIGH. If the first Byte
Enable (B
A
) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
Enable B (B
B
) is LOW, then data from memory will appear on
I/O
8
to I/O
15
. Similarly, B
c
and B
D
correspond to the third and
fourth bytes. See the truth table at the back of this data sheet
for a complete description of read and write modes.
The input/output pins (I/O
0
through I/O
31
) are placed in a
high-impedance state when the device is deselected (CE
1,
CE
2
or CE
3
HIGH), the outputs are disabled (OE HIGH), the
byte selects are disabled (B
A-D
HIGH), or during a write
operation (CE
1,
CE
2
, and CE
3
LOW, and WE LOW).
The CY7C1062AV33 is available in a 119-ball pitch ball grid
array (PBGA) package.
Selection Guide
–8
8
300
300
50
–10
10
275
275
50
–12
12
260
260
50
Unit
ns
mA
Maximum Access Time
Maximum Operating Current
Com
’
l
Ind
’
l
Com
’
l/Ind
’
l
Maximum CMOS Standby Current
mA
Logic Block Diagram
1
A
1
A
A1
A2
A3
A4
A5
A6
A7
A8
A9
COLUMN
DECODER
R
S
INPUT BUFFERS
512K x 32
ARRAY
4096 x 4096
A0
A
A
A
A
A
A
A
I/O
0
–
I/O
31
OE
B
A
B
B
B
C
CE
3
B
D
O
C
WE
CE
1
CE
2
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1062AV33-10BGI | The CY7C1062AV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits. |
| CY7C1062DV33 | 16-Mbit (512K X 32) Static RAM |
| CY7C1062DV33-10BGXI | 16-Mbit (512K X 32) Static RAM |
| CY7C1069AV33-10ZXC | 2M x 8 Static RAM |
| CY7C1069AV33-10ZXI | 2M x 8 Static RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1062AV33-10BGCT | 功能描述:靜態(tài)隨機存取存儲器 512K x 32 Fast Async COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1062AV33-10BGI | 功能描述:靜態(tài)隨機存取存儲器 512K x 32 Fast Async IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1062AV33-10BGIT | 功能描述:靜態(tài)隨機存取存儲器 512K x 32 Fast Async IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1062AV33-12BGC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 16M-Bit 512K x 32 12ns 119-Pin BGA |
| CY7C1062AV33-12BGI | 制造商:Cypress Semiconductor 功能描述: |
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