參數(shù)資料
型號(hào)： CY7C1161V18-300BZI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述： 2M X 8 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165
文件頁(yè)數(shù)： 14/29頁(yè)
文件大小： 659K
代理商： CY7C1161V18-300BZI
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Document Number: 001-06582 Rev. *D
Page 21 of 29
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with Power Applied. –55°C to + 125°C
Supply Voltage on VDD Relative to GND .......–0.5V to + 2.9V
Supply Voltage on VDDQ Relative to GND..... –0.5V to + VDD
DC Applied to Outputs in High Z ........ –0.5V to VDDQ + 0.3V
DC Input Voltage[14]............................... –0.5V to VDD + 0.3V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch up Current.................................................... > 200 mA
Operating Range
Range
Ambient
Temperature (TA)
VDD
VDDQ
Commercial
0°C to +70°C
1.8 ± 0.1V
1.4V to
VDD
Industrial
–40°C to +85°C
Electrical Characteristics
The DC Electrical Characteristics over the operating range follows.[15]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
IO Supply Voltage
1.4
1.5
VDD
V
VOH
Output HIGH Voltage
Note 19
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 20
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH Voltage
IOH = 0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
0.2
V
VIH
Input HIGH Voltage
VREF + 0.1
VDDQ + 0.15
V
VIL
Input LOW Voltage
–0.15
VREF – 0.1
V
IX
Input Leakage Current
GND
≤ V
I ≤ VDDQ
22
μA
IOZ
Output Leakage Current
GND
≤ V
I ≤ VDDQ, Output Disabled
22
μA
VREF
Input Reference Voltage[21]
Typical Value = 0.75V
0.68
0.75
0.95
V
IDD
VDD Operating Supply
VDD = Max, IOUT = 0 mA,
f = fmax = 1/tCYC
300 MHz
850
mA
333 MHz
920
mA
375 MHz
1020
mA
400 MHz
1080
mA
ISB1
Automatic Power Down
Current
Max VDD,
Both Ports Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fmax = 1/tCYC,
Inputs Static
300 MHz
250
mA
333 MHz
260
mA
375 MHz
290
mA
400 MHz
300
mA
AC Electrical Characteristics
Over the operating range follows.[21]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIH
Input HIGH Voltage
VREF + 0.2
–
VDDQ + 0.24
V
VIL
Input LOW Voltage
–0.24
–
VREF – 0.2
V
Notes
18. Power up: Is based upon a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
19. Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
20. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
21. VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.
22. The operation current is calculated with 50% read cycle and 50% write cycle.
相關(guān)PDF資料
PDF描述
CY7C1161V18-333BZI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1161V18-333BZC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1161V18-300BZXI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1161V18-300BZXC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
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