參數(shù)資料
型號(hào)： CY7C1161V18-300BZXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： SRAM
英文描述： 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述： 2M X 8 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPBGA-165
文件頁(yè)數(shù)： 26/29頁(yè)
文件大?。?/td> 659K
代理商： CY7C1161V18-300BZXI
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Document Number: 001-06582 Rev. *D
Page 6 of 29
Pin Definitions
Pin Name
IO
Pin Description
D[x:0]
Input-
Synchronous
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1161V18
D
[7:0]
CY7C1176V18
D
[8:0]
CY7C1163V18
D
[17:0]
CY7C1165V18
D
[35:0]
WPS
Input-
Synchronous
Write Port Select
Active LOW. Sampled on the rising edge of the K clock. When asserted active,
a write operation is initiated. Deasserting deselects the write port. Deselecting the write port causes
D[x:0] to be ignored.
NWS0, NWS1,
Input-
Synchronous
Nibble Write Select 0, 1
Active LOW (CY7C1161V18 Only). Sampled on the rising edge of the
K and K clocks during Write operations. Used to select the nibble that is written into the device. NWS0
controls D[3:0] and NWS1 controls D[7:4].
All the nibble write selects are sampled on the same edge as the data. Deselecting a nibble write
select causes the corresponding nibble of data to be ignored and not written into the device.
BWS0, BWS1,
BWS2, BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3
Active LOW. Sampled on the rising edge of the K and K clocks
during write operations. Used to select the byte that is written into the device during the current portion
of the write operation. Bytes not written remain unaltered.
CY7C1176V18
BWS
0 controls D[8:0].
CY7C1163V18
BWS
0 controls D[8:0] and BWS1 controls D[17:9]..
CY7C1165V18
BWS
0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18], and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
causes the corresponding byte of data to be ignored and not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1161V18, 2M x 9 (4 arrays each of 512K
x 9) for CY7C1176V18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1163V18, and 512K x 36 (4
arrays each of 128K x 36) for CY7C1165V18. Therefore, only 19 address inputs are needed to access
the entire memory array of CY7C1161V18 and CY7C1176V18, 18 address inputs for CY7C1163V18,
and 17 address inputs for CY7C1165V18. These inputs are ignored when the appropriate port is
deselected.
Q[x:0]
Outputs-
Synchronous
Data Output Signals. These pins drive out the requested data during a read operation. Valid data
is driven out on the rising edge of both the K and K clocks during read operations or K and K when
in single clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1161V18
Q
[7:0].
CY7C1176V18
Q
[8:0].
CY7C1163V18
Q
[17:0].
CY7C1165V18
Q
[35:0].
RPS
Input-
Synchronous
Read Port Select
Active LOW. Sampled on the rising edge of positive input clock (K). When active,
a read operation is initiated. Deasserting causes the read port to be deselected. When deselected,
the pending access is enabled to complete and the output drivers are automatically tri-stated following
the next rising edge of the K clock. Each read access consists of a burst of four sequential transfers.
QVLD
Valid Output
Indicator
Valid Output Indicator. Indicates valid output data. QVLD is edge-aligned with CQ and CQ.
K
Input-
Clock
Positive Input Clock Input. Rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous inputs presented to the device and
to drive out data through Q[x:0] when in single clock mode.
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the QDR-II+. The timings for the echo clocks are shown in “Switching Characteristics”
相關(guān)PDF資料
PDF描述
CY7C1161V18-300BZXC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1161V18 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168V18-333BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168V18-333BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1170V18-300BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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