參數(shù)資料
型號: CY7C1161V18
廠商: Cypress Semiconductor Corp.
英文描述: 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 18兆位的國防評估報(bào)告⑩- II SRAM的4字突發(fā)架構(gòu)(2.5周期讀寫延遲)
文件頁數(shù): 27/29頁
文件大小: 956K
代理商: CY7C1161V18
CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 7 of 29
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the QDR-II+. The timings for the echo clocks are shown in “Switching Characteristics”
on page 23.
ZQ
Input
Output Impedance Matching Input. Used to tune the device outputs to the system data bus
impedance. CQ, CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin is connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-
nected.
DOFF
Input
DLL Turn Off
Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned-off operation are different from those listed in this data sheet. For normal
operation, this pin is connected to a pull up through a 10 K
or less pull up resistor. The device
behaves in QDR-I mode when the DLL is turned off. In this mode, the device operates at a frequency
of up to 167 MHz with QDR-I timing.
TDO
Output
TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/36M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/72M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/144M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
N/A
Not connected to the die. Can be tied to any voltage level.
VREF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and
AC measurement points.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name
IO
Pin Description
[+] Feedback
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