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參數(shù)資料
| 型號(hào)： | CY7C1176V18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 18兆位的國(guó)防評(píng)估報(bào)告⑩- II SRAM的4字突發(fā)架構(gòu)（2.5周期讀寫(xiě)延遲） |
| 文件頁(yè)數(shù)： | 3/29頁(yè) |
| 文件大?。?/td> | 956K |
| 代理商： | CY7C1176V18 |
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CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 3 of 29
Logic Block Diagram (CY7C1163V18)
Logic Block Diagram (CY7C1165V18)
2
CLK
Gen.
A
(17:0)
K
K
Control
Logic
Address
Register
D
[17:0]
R
Read Data Reg.
RPS
WPS
BWS
[1:0]
Q
[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
18
72
18
V
REF
W
Write
Reg
36
A
(17:0)
18
2
2
2
Write
Reg
Write
Reg
Write
Reg
18
CQ
CQ
DOFF
QVLD
1
CLK
Gen.
A
(16:0)
K
K
Control
Logic
Address
Register
D
[35:0]
R
Read Data Reg.
RPS
WPS
BWS
[3:0]
Q
[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
17
36
144
36
V
REF
W
Write
Reg
72
A
(16:0)
17
1
1
1
Write
Reg
Write
Reg
Write
Reg
36
CQ
CQ
DOFF
QVLD
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1176V18-300BZC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-300BZI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-300BZXC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-300BZXI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-333BZC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1214F-100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1214F-100ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215F-166AC | 制造商:Rochester Electronics LLC 功能描述:1MB (32K X 32) 3.3V PIPELINE SCD - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1MBIT 32KX32 3.5NS 100TQFP - Bulk |
| CY7C1217H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 1.125MBIT 32KX36 7.5NS 100TQFP - Bulk |
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