參數(shù)資料
型號： CY7C1177V18-300BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述： 2M X 9 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù)： 3/27頁
文件大?。?/td> 648K
代理商： CY7C1177V18-300BZC
CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
Document Number: 001-06620 Rev. *D
Page 11 of 27
The write cycle descriptions of CY7C1170V18 follows. [2, 8]
BWS0
BWS1
BWS2
BWS3
K
Comments
LLLL
L-H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
LLLL
–
L-H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
L-H
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
H
–
L-H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
L
H
L-H
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H
L
H
–
L-H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H
L
H
L-H
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
L
H
–
L-H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
L
L-H
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
L
–
L-H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
HHHH
L-H
–
No data is written into the device during this portion of a write operation.
HHHH
–
L-H No data is written into the device during this portion of a write operation.
相關(guān)PDF資料
PDF描述
CY7C1177V18-300BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-300BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-300BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-333BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-333BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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