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參數(shù)資料
| 型號： | CY7C1338G-117BGC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (128K x 32) Flow-Through Sync SRAM |
| 中文描述： | 4兆位（128K的× 32）流量通過同步SRAM的 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 291K |
| 代理商： | CY7C1338G-117BGC |
PRELIMINARY
CY7C1338G
Document #: 38-05521 Rev. *A
Page 3 of 17
Pin Definitions
Name
I/O
Input-
Description
A0, A1, A
Synchronous
Address Inputs used to select one of the 128K address location
s. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3
are sampled active. A
[1:0]
feed
the 2-bit counter.
Byte Write Select Inputs, active LOW
. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW
. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
[A:D]
and BWE).
Byte Write Enable Input, active LOW
. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Input-Clock
Clock Input
. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
Synchronous
CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only
when a new external address is loaded.
Input-
Synchronous
CE
1
and CE
3
to select/deselect the device. CE
2
is sampled only when a new external address is
loaded.
Input-
Synchronous
CE
1
and CE
2
to select/deselect the device. CE
3
is sampled only when a new external address is
loaded.
Input-
Asynchronous
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected
state.
Input-
Synchronous
increments the address in a burst cycle.
BW
A,
BW
B
BW
C,
BW
D
GW
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
BWE
CLK
CE
1
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction with
CE
2
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used in conjunction with
CE
3
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction with
OE
Output Enable, asynchronous input, active LOW
. Controls the direction of the I/O pins. When
ADV
Advance Input signal, sampled on the rising edge of CLK
. When asserted, it automatically
Pin Configurations
(continued)
2
A
3
A
A
A
4
5
A
A
6
A
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
C
DQ
C
V
DDQ
DQ
C
NC
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
NC
DQ
D
DQ
D
NC
NC
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
ADSP
ADSC
V
DDQ
NC
NC
DQ
B
DQ
B
CE
2
A
V
DDQ
V
DDQ
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
V
DD
A
V
SS
V
SS
BW
C
V
SS
MODE
V
SS
V
SS
V
SS
BW
D
V
SS
NC
V
SS
NC
NC
A
NC
NC
NC
NC
NC
NC
NC
ZZ
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
A
A
NC
A
NC
A
A
A0
A1
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
NC
DQ
A
DQ
A
DQ
A
V
SS
V
SS
V
SS
BW
B
V
SS
NC
V
SS
BW
A
V
SS
V
SS
V
SS
BWE
119-Ball BGA
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1338S-100AXC | 功能描述:靜態(tài)隨機存取存儲器 CY7C1338S-100AXC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1338S-100AXCT | 功能描述:靜態(tài)隨機存取存儲器 CY7C1338S-100AXCT RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1339-166AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1339A-100AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:4MB (128K X 32 )- BURST SYNCHROUNOUS PIPELINE SRAM - Bulk 制造商:Cypress Semiconductor 功能描述:128KX32 4M PIPELINE 3.3V CACHE 100.000 MHZ |
| CY7C1339A-100ACT | 制造商:Cypress Semiconductor 功能描述:4M- 128KX32 3.3V PIPELINE 1CD-SYNCHRONOUS SRAM - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:4M- 128KX32 3.3V PIPELINE 1CD-SYNCHRONOUS SRAM - Tape and Reel |
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