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參數(shù)資料
| 型號： | CY7C1338G-117BGC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (128K x 32) Flow-Through Sync SRAM |
| 中文描述： | 4兆位（128K的× 32）流量通過同步SRAM的 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 291K |
| 代理商： | CY7C1338G-117BGC |
PRELIMINARY
CY7C1338G
Document #: 38-05521 Rev. *A
Page 6 of 17
Truth Table
[2, 3, 4, 5, 6]
Cycle Description
Address
Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
1
CE
2
CE
3
ZZ ADSP ADSC
H
X
X
L
L
L
X
L
L
X
H
L
L
L
X
L
X
X
X
L
X
X
X
H
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
X
X
X
L
X
X
X
L
H
X
X
L
H
X
X
L
X
X
X
L
H
X
X
L
X
X
X
L
X
X
X
L
H
X
X
L
H
X
X
L
X
X
X
L
H
X
X
L
ADV
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE OE CLK
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
DQ
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Snooze Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
L-H tri-state
L-H tri-state
L-H tri-state
L-H tri-state
L-H tri-state
X
tri-state
L-H Q
L-H tri-state
L-H D
L-H Q
L-H tri-state
L-H Q
L-H tri-state
L-H Q
L-H tri-state
L-H D
L-H D
L-H Q
L-H tri-state
L-H Q
L-H tri-state
L-H D
L-H D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW
A
, BW
B
, BW
C
, BW
D
) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
(BW
, BW
, BW
, BW
), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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| CY7C1338S-100AXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 CY7C1338S-100AXC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1338S-100AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 CY7C1338S-100AXCT RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1339-166AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1339A-100AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:4MB (128K X 32 )- BURST SYNCHROUNOUS PIPELINE SRAM - Bulk 制造商:Cypress Semiconductor 功能描述:128KX32 4M PIPELINE 3.3V CACHE 100.000 MHZ |
| CY7C1339A-100ACT | 制造商:Cypress Semiconductor 功能描述:4M- 128KX32 3.3V PIPELINE 1CD-SYNCHRONOUS SRAM - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:4M- 128KX32 3.3V PIPELINE 1CD-SYNCHRONOUS SRAM - Tape and Reel |
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