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參數(shù)資料
| 型號： | CY7C1347G-200BGXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (128K x 36) Pipelined Sync SRAM |
| 中文描述： | 128K X 36 CACHE SRAM, 2.8 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 841K |
| 代理商： | CY7C1347G-200BGXI |
CY7C1347G
Document #: 38-05516 Rev. *E
Page 7 of 21
to the DQs and DQPs inputs. Doing so tri-states the output
drivers. As a safety precaution, DQs and DQPs are automati-
cally tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Burst Sequences
The CY7C1347G provides a two-bit wraparound counter, fed
by A
[1:0]
, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user-selectable
through the MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected before entering
the “sleep” mode. CE
1
, CE
2
, CE
3
, ADSP, and ADSC must
remain inactive for the duration of t
ZZREC
after the ZZ input
returns LOW.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A
[1:0]
00
A
[1:0]
01
A
[1:0]
10
A
[1:0]
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A
[1:0]
00
A
[1:0]
01
A
[1:0]
10
A
[1:0]
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
ZZ > V
DD
0.2V
ZZ > V
DD
0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min
Max
40
2t
CYC
Unit
mA
ns
ns
ns
ns
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
2t
CYC
2t
CYC
0
[+] Feedback
相關(guān)PDF資料 |
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| CY7C1347G | 4-Mbit (128K x 36) Pipelined Sync SRAM |
| CY7C1347G-133AXC | 4-Mbit (128K x 36) Pipelined Sync SRAM |
| CY7C1347G-133AXI | 4-Mbit (128K x 36) Pipelined Sync SRAM |
| CY7C1347G-133BGC | 4-Mbit (128K x 36) Pipelined Sync SRAM |
| CY7C1347G-133BGI | 4-Mbit (128K x 36) Pipelined Sync SRAM |
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| CY7C1347G-250AXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 128Kx36 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1347G-250AXCT | 功能描述:IC SRAM 4.5MBIT 250MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動(dòng) SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C1347G-BGXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1347S-133AXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 CY7C1347S-133AXC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1347S-133AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 CY7C1347S-133AXCT RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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