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| 型號(hào)： | CY7C1362B-200BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| 中文描述： | 512K X 18 CACHE SRAM, 3 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165 |
| 文件頁(yè)數(shù)： | 25/34頁(yè) |
| 文件大?。?/td> | 895K |
| 代理商： | CY7C1362B-200BZI |
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CY7C1360B
CY7C1362B
Document #: 38-05291 Rev. *C
Page 25 of 34
Switching Characteristics
Over the Operating Range
[16, 17]
Parameter
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
ADVH
t
WEH
t
DH
t
CEH
Shaded areas contain advance information.
Description
225 MHz
Min.
1
200 MHz
Min.
1
166 MHz
Min.
1
Unit
ms
Max
Max
Max
V
DD
(Typical) to the First Access
[18]
Clock Cycle Time
Clock HIGH
Clock LOW
4.4
1.8
1.8
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z
[19, 20, 21]
Clock to High-Z
[19, 20, 21]
OE LOW to Output Valid
OE LOW to Output Low-Z
[19, 20, 21]
OE HIGH to Output High-Z
[19, 20, 21]
2.8
3.0
3.5
ns
ns
ns
ns
ns
ns
ns
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
2.8
2.8
3.0
3.0
3.5
3.5
0
0
0
2.8
3.0
3.5
Address Set-up before CLK Rise
ADSC, ADSP Set-up before CLK Rise
ADV Set-up before CLK Rise
GW, BWE, BW
X
Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Address Hold after CLK Rise
ADSP , ADSC Hold after CLK Rise
ADV Hold after CLK Rise
GW,BWE, BW
X
Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Notes:
16.Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a Read or Write operation
can be initiated.
19.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
21.This parameter is sampled and not 100% tested.
相關(guān)PDF資料 |
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| CY7C1362B-200BZC | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| CY7C1362B-200BGI | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| CY7C1362B-225AJC | BACKSHELL, MDR, 50WAY, METAL; For use with:Mini D Ribbon 101XX-6000 EC Plug Connectors; Material:Aluminum; Colour:Nickel; Connector type:Backshell; Ways, No. of:50 RoHS Compliant: Yes |
| CY7C1362B-225AI | Plastic Connector Backshell; Connector Shell Size:Black; Enclosure Material:Polyester; Enclosure Color:Black; Features:For: 0.050" D-Miniature D Ribbon Connectors; Leaded Process Compatible:No; No. of Positions:50 RoHS Compliant: No |
| CY7C1362B-225AJI | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
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| CY7C1362C-166AJXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx18 3.3V COM Sync PL 1CD 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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| CY7C1362C-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 9M-Bit 512K x 18 3.5ns 100-Pin TQFP |
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