參數(shù)資料
型號(hào): CY7C1362B-225BGC
廠(chǎng)商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
中文描述: 512K X 18 CACHE SRAM, 2.8 ns, PBGA119
封裝: 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
文件頁(yè)數(shù): 24/34頁(yè)
文件大?。?/td> 895K
代理商: CY7C1362B-225BGC
CY7C1360B
CY7C1362B
Document #: 38-05291 Rev. *C
Page 24 of 34
Thermal Resistance
[15]
Parameter
Θ
JA
Description
Test Conditions
TQFP
Package
BGA
Package
fBGA
Package
Unit
°
C/W
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA / JESD51.
25
25
27
Θ
JC
Thermal Resistance
(Junction to Case)
9
6
6
°
C/W
Capacitance
[15]
Parameter
Description
Test Conditions
TQFP
Package
BGA
Package
fBGA
Package
Unit
C
IN
Input Capacitance
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 3.3V.
V
DDQ
= 2.5V
5
5
5
pF
C
CLK
Clock Input Capacitance
5
5
5
pF
C
I/O
Input/Output Capacitance
5
7
7
pF
AC Test Loads and Waveforms
Note:
15.Tested initially and after any design or process change that may affect these parameters.
OUTPUT
R = 317
R = 351
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
L
= 1.5V
3.3V
ALL INPUT PULSES
V
DD
GND
90%
10%
90%
10%
1 ns
1 ns
(c)
OUTPUT
R = 1667
R =1538
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
L
= 1.25V
2.5V
ALL INPUT PULSES
V
DD
GND
90%
10%
90%
10%
1 ns
1 ns
(c)
3.3V I/O Test Load
2.5V I/O Test Load
相關(guān)PDF資料
PDF描述
CY7C1362B-225AC 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1362B Plastic Connector Backshell; Enclosure Material:Plastic; Enclosure Color:Beige; Leaded Process Compatible:No; No. of Positions:26; Peak Reflow Compatible (260 C):No RoHS Compliant: No
CY7C43686AV-15AC 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO
CY7C43686AV-7AC 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO
CY7C43686AV-10AI 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO
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