參數(shù)資料
型號: CY7C1380BV25-200BGC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 512K x 36 / 1 Mb x 18 Pipelined SRAM
中文描述: 512K X 36 CACHE SRAM, 3 ns, PBGA119
封裝: 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
文件頁數(shù): 8/30頁
文件大小: 860K
代理商: CY7C1380BV25-200BGC
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
8
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CEs, ADSP and ADSC must remain inactive for the duration
of t
ZZREC
after the ZZ input returns LOW.
Interleaved Burst Sequence
First
Address
A
[1:0]]
00
01
10
11
Second
Address
A
[1:0]
01
00
11
10
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
10
01
00
Linear Burst Sequence
First
Address
A
[1:0]
00
01
10
11
Second
Address
A
[1:0]
01
10
11
00
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
I
DDZZ
Snooze mode
standby current
ZZ
>
V
DD
0.2V
15
mA
t
ZZS
Device operation to
ZZ
ZZ
>
V
DD
0.2V
2t
CYC
ns
t
ZZREC
ZZ recovery time
ZZ
<
0.2V
2t
CYC
ns
相關(guān)PDF資料
PDF描述
CY7C1382BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM
CY7C1382BV25-133AC 512K x 36 / 1 Mb x 18 Pipelined SRAM
CY7C1382BV25-133BGC 512K x 36 / 1 Mb x 18 Pipelined SRAM
CY7C1381C 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-117AC 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
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