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參數(shù)資料
| 型號： | CY7C1382BV25-133AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 36 / 1 Mb x 18 Pipelined SRAM |
| 中文描述： | 1M X 18 CACHE SRAM, 4.2 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 1/30頁 |
| 文件大?。?/td> | 860K |
| 代理商： | CY7C1382BV25-133AC |
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512K x 36 / 1 Mb x 18 Pipelined SRAM
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), burst control in-
puts (ADSC, ADSP and ADV), Write Enables (BWa, BWb,
BWc, BWd and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and Burst
Mode Control (MODE). The data (DQ
a,b,c,d
) and the data par-
ity (DQP
a,b,c,d
) outputs, enabled by OE, are also asynchro-
nous.
DQ
a,b,c,d
and DQP
a,b,c,d
apply to CY7C1380BV25 and DQ
a,b
and DQP
a,b
apply to CY7C1382BV25. a, b, c, d each are of 8
bits wide in the case of DQ and 1 bit wide in the case of DP
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DQPa. BWb controls DQb and DQPb. BWc
controls DQc and DQPd. BWd controls DQd-DQd and DQPd.
BWa, BWb BWc, and BWd can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. WRITE
pass-through capability allows written data available at the out-
put for the immediately next READ cycle. This device also in-
corporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
All inputs and outputs of the CY7C1380BV25 and the
CY7C1382BV25 are JEDEC standard JESD8-5 compatible.
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
July 5, 2001
1CY7C1380BV25
Features
Fast clock speed: 200,166, 150, 133 MHz
Provide high-performance 3-1-1-1 access rate
Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns
Optimal for depth expansion
2.5V (±5%) Operation
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed WRITE CYCLE
Burst control pins (interleaved or linear burst se-
quence)
Automatic power-down for portable applications
High-density, high-speed packages
JTAG boundary scan for BGA packaging version
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced sin-
gle-layer polysilicon, triple-layer metal technology. Each mem-
ory cell consists of six transistors.
The CY7C1382BV25 and CY7C1380BV25 SRAMs integrate
1,048,576x18 and 524,288x36 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
isters controlled by a positive-edge-triggered clock input
Selection Guide
200 MHz
166 MHz
150 MHz
133 MHz
Maximum Access Time (ns)
3.0
3.4
3.8
4.2
Maximum Operating Current (mA)
Commercial
280
230
190
160
Maximum CMOS Standby Current (mA)
30
30
30
30
Shaded areas contain advance information.
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1382BV25-133BGC | 512K x 36 / 1 Mb x 18 Pipelined SRAM |
| CY7C1381C | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381C-117AC | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381C-117AI | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381C-117BGC | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1382C-167AC | 功能描述:IC SRAM 18MBIT 167MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 |
| CY7C1382C-200AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1382C-200BZC | 制造商:Rochester Electronics LLC 功能描述:16MB (1MX18) 3.3V SYNC-PIPE (SINGLE CYCLE DESELECT) SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1382C-225AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1382D-167AXC | 功能描述:靜態(tài)隨機存取存儲器 1Mx18 3.3V COM 1CD Sync PL 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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