- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378502 > CY7C1380BV25 (Cypress Semiconductor Corp.) 512K x 36 / 1 Mb x 18 Pipelined SRAM PDF資料下載
參數(shù)資料
| 型號： | CY7C1380BV25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512K x 36 / 1 Mb x 18 Pipelined SRAM |
| 中文描述： | 為512k × 36 / 1字節(jié)× 18流水線的SRAM |
| 文件頁數(shù)： | 5/30頁 |
| 文件大?。?/td> | 860K |
| 代理商： | CY7C1380BV25 |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
5
Pin Definitions
Name
I/O
Input-
Description
A0
A1
A
BWa
BWb
BWc
BWd
GW
Synchronous
Address Inputs used to select one of the address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1,
CE
2,
and
CE
3
are sampled active. A
[1:0]
feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
Input-
Synchronous
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless of
the values on BW
a,b,c,d
and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ig-
nored if CE
1
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE
1
and CE
3
to select/deselect the device. (TQFP Only)
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE
1
and
CE
2
to select/deselect the device.
(TQFP Only)
Output Enable, asynchronous input, active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH,
I/O pins are three-stated, and act as input data pins. OE is masked during the
first clock of a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When
asserted LOW, A is captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When
asserted LOW, A
[x:0]
is captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized.
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to V
DDQ
or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A during the previous clock rise
of the read cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx
are
placed in a three-state condition.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK
(BGA Only).
BWE
Input-
Synchronous
Input-Clock
CLK
CE
1
Input-
Synchronous
CE
2
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CE
3
OE
ADV
Input-
Synchronous
Input-
Synchronous
ADSP
ADSC
Input-
Synchronous
MODE
Input-
Static
ZZ
Input-
Asynchronous
I/O-
Synchronous
DQa, DQPa
DQb, DQPb
DQc, DQPc
DQd, DQPd
TDO
JTAG serial
output
Synchronous
JTAG serial
input
Synchronous
TDI
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA
Only).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1380BV25-133AC | 512K x 36 / 1 Mb x 18 Pipelined SRAM |
| CY7C1380BV25-150AC | 512K x 36 / 1 Mb x 18 Pipelined SRAM |
| CY7C1380BV25-150BGC | 512K x 36 / 1 Mb x 18 Pipelined SRAM |
| CY7C1380BV25-166AC | 512K x 36 / 1 Mb x 18 Pipelined SRAM |
| CY7C1380BV25-166BGC | 512K x 36 / 1 Mb x 18 Pipelined SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1380BV25-200AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1380C-133AC | 功能描述:IC SRAM 18MBIT 133MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1380C-150AC | 制造商:Cypress Semiconductor 功能描述:16MB (512KX36) 3.3V SYNC-PIPE (SINGLE CYCLE DESELECT) SRAM - Bulk |
| CY7C1380C-167AC | 功能描述:IC SRAM 18MBIT 167MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1380C-167BGC | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。