參數(shù)資料
型號(hào): CY7C1381C-133AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
中文描述: 512K X 36 STANDARD SRAM, 6.5 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁(yè)數(shù): 11/36頁(yè)
文件大?。?/td> 564K
代理商: CY7C1381C-133AC
CY7C1381C
CY7C1383C
Document #: 38-05238 Rev. *B
Page 11 of 36
V
DD
15,41,65,91
C4,J2,J4,J6,R4
D4,D8,E4,
E8,F4,F8,
G4,G8,
H4,H8,J4,
J8,K4,K8,
L4,L8,M4,
M8
Power Supply
Power supply inputs to the core of the
device
.
V
DDQ
4,11,20,27,
54,61,70,77
A1,A7,F1,F7,J1,
J7,M1,M7,U1,U
7
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
I/O Power
Supply
Power supply for the I/O circuitry
.
V
SS
17,40,67,90
D3,D5,E3,E5,F3
,F5,G5,H3,
H5,K3,K5,L3,M3
,
M5,N3,
N5,P3,P5
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
E6,E7,F5,
F6,F7,G5,
G6,G7,H1,
H2,H5,H6,
H7,J5,J6,J7,K5,
K6,K7,L5,L6,L7,
M5,
M6,M7,N4,
N8
Ground
Ground for the core of the device
.
V
SSQ
5,10,21,26,
55,60,71,76,
-
-
I/O Ground
Ground for the I/O circuitry
.
TDO
-
U5
P7
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit
.
Delivers data on the negative edge of TCK.
If the JTAG feature is not being utilized, this
pin should be left unconnected. This pin is
not available on TQFP packages.
TDI
-
U3
P5
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit
.
Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin
can be left floating or connected to V
DD
through a pull up resistor. This pin is not
available on TQFP packages.
TMS
-
U2
R5
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit
.
Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin
can be disconnected or connected to V
DD
.
This pin is not available on TQFP packages.
TCK
-
U4
R7
JTAG-Clock
Clock input to the JTAG circuitry
. If the
JTAG feature is not being utilized, this pin
must be connected to V
SS
. This pin is not
available on TQFP packages.
CY7C1383C:Pin Definitions
(continued)
Name
TQFP
(3-Chip
Enable)
BGA
(1-Chip
Enable)
fBGA
(3-Chip
Enable)
I/O
Description
相關(guān)PDF資料
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CY7C1381C-133BGC 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-133BZC 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
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