參數(shù)資料
型號(hào)： CY7C1411BV18
廠商： Cypress Semiconductor Corp.
英文描述： 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
中文描述： 36兆位的國(guó)防評(píng)估報(bào)告⑩- II SRAM的4字突發(fā)結(jié)構(gòu)
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 1644K
代理商： CY7C1411BV18
PRELIMINARY
CY7C1411BV18
CY7C1426BV18
CY7C1413BV18
CY7C1415BV18
Document Number: 001-07037 Rev. *B
Page 7 of 28
Functional Overview
The CY7C1411BV18, CY7C1426BV18, CY7C1413BV18,
CY7C1415BV18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-II completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of four 8-bit data transfers in the case of
CY7C1411BV18, four 9-bit data transfers in the case of
CY7C1426BV18, four 18-bit data transfers in the case of
CY7C1413BV18, and four 36-bit data in the case of
CY7C1415BV18 transfers in two clock cycles.
This device operates with a read latency of one and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to V
SS
then device will behave in QDR-I mode with
a read latency of one clock cycle.
Accesses for both ports are initiated on the Positive Input
Clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the output clocks (C and C or K and K when
in single clock mode).
All synchronous data inputs (D
[x:0]
) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q
[x:0]
) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single-clock mode).
All synchronous control (RPS, WPS, BWS
[x:0]
) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1413BV18 is described in the following sections. The
same
basic
descriptions
CY7C1426BV18, and CY7C1415BV18.
apply
to
CY7C1411BV18,
Read Operations
The CY7C1413BV18 is organized internally as 4 arrays of
512K x 18. Accesses are completed in a burst of four
sequential 18-bit data words. Read operations are initiated by
asserting RPS
active at the rising edge of the Positive Input
CQ
Echo Clock
CQ is referenced with respect to C
. This is a free running clock and is synchronized to the Input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
CQ
Echo Clock
CQ is referenced with respect to C
. This is a free running clock and is synchronized to the Input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
ZQ
Input
Output Impedance Matching Input
. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to
V
DDQ
, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF
Input
DLL Turn Off - Active LOW
. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
For normal operation, this pin can be connected to a pull-up through a 10-Kohm or less pull-up
resistor. The device will behave in QDR-I mode when the DLL is turned off. In this mode, the
device can be operated at a frequency of up to 167 MHz with QDR-I timing.
TDO
Output
TDO for JTAG
.
TCK
Input
TCK pin for JTAG
.
TDI
Input
TDI pin for JTAG
.
TMS
Input
TMS pin for JTAG
.
NC
N/A
Not connected to the die
. Can be tied to any voltage level.
NC/72M
N/A
Not connected to the die
. Can be tied to any voltage level.
NC
/144M
N/A
Not connected to the die
. Can be tied to any voltage level.
NC
/288M
N/A
Not connected to the die
. Can be tied to any voltage level.
V
REF
Input-
Reference
Reference Voltage Input
. Static input used to set the reference level for HSTL inputs and outputs
as well as AC measurement points.
V
DD
V
SS
V
DDQ
Power Supply
Power supply inputs to the core of the device
.
Ground
Ground for the device
.
Power Supply
Power supply inputs for the outputs of the device
.
Pin Definitions
(continued)
Pin Name
I/O
Pin Description
相關(guān)PDF資料
PDF描述
CY7C1415BV18 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
CY7C145 8K x 8 Dual-Port Static RAM(8K x 8 雙端口靜態(tài) RAM)
CY7C144 8K x 9 Dual-Port Static RAM(8K x 9 雙端口靜態(tài) RAM)
CY7C146-25JC 2Kx8 Dual-Port Static RAM
CY7C146-30JC 2Kx8 Dual-Port Static RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1411BV18-250BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx36 QDR II Burst 4 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1411KV18-250BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36Mb QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1411KV18-300BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB (4Mx8) 1.8v 300MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1411SC 制造商:Cypress Semiconductor 功能描述:
CY7C1411SV18-250BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 NV靜態(tài)隨機(jī)存取存儲(chǔ)器 250 MHz 1.8V RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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