參數(shù)資料
型號(hào)： CY7C1413AV18-300BZXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
中文描述： 2M X 18 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 1143K
代理商： CY7C1413AV18-300BZXI
CY7C1411AV18
CY7C1426AV18
CY7C1413AV18
CY7C1415AV18
Document Number: 38-05614 Rev. *C
Page 7 of 28
Functional Overview
The CY7C1411AV18, CY7C1426AV18, CY7C1413AV18,
CY7C1415AV18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-II completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of four 8-bit data transfers in the case of
CY7C1411AV18, four 9-bit data transfers in the case of
CY7C1426AV18, four 18-bit data transfers in the case of
CY7C1413AV18, and four 36-bit data in the case of
CY7C1415AV18 transfers in two clock cycles.
Accesses for both ports are initiated on the Positive Input
Clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the output clocks (C and C or K and K when
in single clock mode).
All synchronous data inputs (D
[x:0]
) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q
[x:0]
) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single-clock mode).
All synchronous control (RPS, WPS, BWS
[x:0]
) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1413AV18 is described in the following sections. The
same
basic
descriptions
CY7C1426AV18, and CY7C1415AV18.
apply
to
CY7C1411AV18,
Read Operations
The CY7C1413AV18 is organized internally as 4 arrays of
512K x 18. Accesses are completed in a burst of four
sequential 18-bit data words. Read operations are initiated by
asserting RPS
active at the rising edge of the Positive Input
Clock (K). The address presented to Address inputs are stored
in the Read address register. Following the next K clock rise,
the corresponding lowest order 18-bit word of data is driven
onto the Q
[17:0]
using C as the output timing reference. On the
subsequent rising edge of C the next 18-bit data word is driven
onto the Q
[17:0]
. This process continues until all four 18-bit data
words have been driven out onto Q
[17:0]
. The requested data
will be valid 0.45 ns from the rising edge of the output clock (C
or C or (K or K when in single-clock mode)). In order to
maintain the internal logic, each read access must be allowed
to complete. Each Read access consists of four 18-bit data
CQ
Echo Clock
CQ is referenced with respect to C
. This is a free running clock and is synchronized to the Input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
CQ
Echo Clock
CQ is referenced with respect to C
. This is a free running clock and is synchronized to the Input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
Output Impedance Matching Input
. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
V
DDQ
, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DLL Turn Off - active LOW
. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
TDO for JTAG
.
TCK pin for JTAG
.
TDI pin for JTAG
.
TMS pin for JTAG
.
Not connected to the die
. Can be tied to any voltage level.
Not connected to the die
. Can be tied to any voltage level.
Not connected to the die
. Can be tied to any voltage level.
Not connected to the die
. Can be tied to any voltage level.
Reference Voltage Input
. Static input used to set the reference level for HSTL inputs and outputs
as well as AC measurement points.
Power Supply
Power supply inputs to the core of the device
.
Ground
Ground for the device
.
Power Supply
Power supply inputs for the outputs of the device
.
ZQ
Input
DOFF
Input
TDO
TCK
TDI
TMS
NC
NC/72M
NC
/144M
NC
/288M
V
REF
Output
Input
Input
Input
N/A
N/A
N/A
N/A
Input-
Reference
V
DD
V
SS
V
DDQ
Pin Definitions
(continued)
Pin Name
I/O
Pin Description
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1415AV18-167BZC 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
CY7C1415AV18-167BZI 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
CY7C1415AV18-167BZXC 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
CY7C1415AV18-167BZXI 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
CY7C1415AV18-200BZC 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1413BV18-200BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx18 QDR II Burst 4 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1413BV18-250BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx18 QDR II Burst 4 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1413JV18-200BZXI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx18 QDR-II BURST 4 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1413JV18-250BZI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx18 QDR-II Burst 4 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1413JV18-250BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36-Mbit QDR 靜態(tài)隨機(jī)存取存儲(chǔ)器 4-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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