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參數(shù)資料
| 型號： | CY7C1414BV18-167BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 1M X 36 QDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 1072K |
| 代理商： | CY7C1414BV18-167BZXI |
PRELIMINARY
CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
Document #: 001-07036 Rev. *B
Page 9 of 26
Application Example
[1]
Truth Table for DDR-II
[2, 3, 4, 5, 6, 7]
Operation
K
RPS
X
WPS
L
DQ
DQ
Write Cycle:
Load address on the rising edge of K clock; input
write data on K and K rising edges.
Read Cycle:
Load address on the rising edge of K clock; wait one
and a half cycle; read data on C and C rising edges.
NOP: No Operation
L-H
D(A + 0) at K(t)
↑
D(A + 1) at K(t)
↑
L-H
L
X
Q(A + 0) at C(t + 1)
↑
Q(A + 1) at C(t + 2)
↑
L-H
H
H
D = X
Q = High-Z
Previous State
D = X
Q = High-Z
Previous State
Standby: Clock Stopped
Stopped
X
X
Notes:
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,
↑
represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 00, A + 01 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
C
C#
D
A
K
C
C#
D
A
K
BUS
MASTER
(CPU
or
ASIC)
SRAM #1
SRAM #4
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K#
R = 50
οημσ
R = 250
οημσ
R = 250
οημσ
R
P
S
#
W
P
S
#
B
W
S
#
R
P
S
#
W
P
S
#
B
W
S
#
Vt
Vt
Vt
R
R
R
ZQ
CQ/CQ#
Q
K#
ZQ
CQ/CQ#
Q
K#
CLKIN/CLKIN#
[+] Feedback
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| CY7C1414BV18-200BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1414BV18-200BZI | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1414BV18-200BZXI | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1414BV18-250BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1414BV18-250BZXI | 功能描述:靜態(tài)隨機存取存儲器 36-Mbit QDR-II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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