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參數(shù)資料
| 型號： | CY7C1414BV18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 的36 - Mbit QDR - II型⑩SRAM的2字突發(fā)結(jié)構(gòu) |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 1072K |
| 代理商： | CY7C1414BV18 |
PRELIMINARY
CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
Document #: 001-07036 Rev. *B
Page 7 of 26
Functional Overview
The CY7C1410BV18, CY7C1425BV18, CY7C1412BV18 and
CY7C1414BV18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-II completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of two 8-bit data transfers in the case of
CY7C1410BV18, two 9-bit data transfers in the case of
CY7C1425BV18,two 18-bit data transfers in the case of
CY7C1412BV18 and two 36-bit data transfers in the case of
CY7C1414BV18, in one clock cycle.
This device operates with a read latency of one and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to V
SS
then device will behave in QDR-I mode with
a read latency of one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the input clocks (K and K)
and all output timings are referenced to the rising edge of
output clocks (C and C or K and K when in single clock mode).
All synchronous data inputs (D
[x:0]
) inputs pass through input
registers controlled by the input clocks (K and K). All
K
Input-Clock
Positive Input Clock Input
. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q
[x:0]
when in single clock mode. All accesses
are initiated on the rising edge of K.
Negative Input Clock Input
. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q
[x:0]
when in single clock mode.
CQ is referenced with respect to C
. This is a free running clock and is synchronized
to the Input clock for output data (C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K. The timings for the echo clocks are shown in the AC Timing
table.
CQ is referenced with respect to C
. This is a free running clock and is synchronized
to the Input clock for output data (C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K. The timings for the echo clocks are shown in the AC Timing
table.
Output Impedance Matching Input
. This input is used to tune the device outputs to the
system data bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be
connected directly to V
DDQ
, which enables the minimum impedance mode. This pin
cannot be connected directly to GND or left unconnected.
DLL Turn Off - Active LOW
. Connecting this pin to ground will turn off the DLL inside
the device. The timings in the DLL turned off operation will be different from those listed
in this data sheet. For normal operation, this pin can be connected to a pull-up through
a 10-Kohm or less pull-up resistor. The device will behave in DDR-I mode when the DLL
is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR-I timing.
TDO for JTAG
.
TCK pin for JTAG
.
TDI pin for JTAG
.
TMS pin for JTAG
.
Not connected to the die
. Can be tied to any voltage level.
Not connected to the die
. Can be tied to any voltage level.
Not connected to the die
. Can be tied to any voltage level.
Not connected to the die
. Can be tied to any voltage level.
Reference Voltage Input
. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
Power supply inputs to the core of the device
.
Ground for the device
.
Power supply inputs for the outputs of the device
.
K
Input-Clock
CQ
Echo Clock
CQ
Echo Clock
ZQ
Input
DOFF
Input
TDO
TCK
TDI
TMS
NC
NC/72M
NC/144M
NC/288M
V
REF
Output
Input
Input
Input
N/A
N/A
N/A
N/A
Input-
Reference
Power Supply
Ground
Power Supply
V
DD
V
SS
V
DDQ
Pin Definitions
(continued)
Pin Name
I/O
Pin Description
[+] Feedback
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| CY7C1414BV18-167BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1414BV18-200BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1414BV18-200BZI | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1414BV18-200BZXI | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1414BV18-250BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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