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參數(shù)資料
| 型號(hào)： | CY7C143-25JI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2K x 16 Dual-Port Static RAM |
| 中文描述： | 2K X 16 DUAL-PORT SRAM, 25 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 506K |
| 代理商： | CY7C143-25JI |
CY7C133
CY7C143
Document #: 38-06036 Rev. *B
Page 7 of 13
Switching Characteristics
Over the Operating Range
[9]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[14]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Busy/Interrupt Timing (for master CY7C133)
t
BLA
BUSY Low from Address Match
t
BHA
BUSY High from Address Mismatch
t
BLC
BUSY Low from CE LOW
t
BHC
BUSY High from CE HIGH
t
WDD
t
DDD
t
BDD
t
PS
Busy Timing (for slave CY7C143)
t
WB
t
WH
t
WDD
t
DDD
Notes:
9.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
/I
and 30-pF load capacitance.
10. AC Test Conditions use V
= 1.6V and V
= 1.4V.
11.
At any given temperature and voltage condition for any given device, t
is less than t
and t
is less than t
.
12. t
, t
, t
, t
, t
and t
are tested with C
L
= 5 pF as in part (b) of AC Test Loads
.
Transition is measured ±500 mV from steady state voltage.
13. This parameter is guaranteed but not tested.
14. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
15. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with BUSY, Master: CY7C133.”
16. t
is a calculated parameter and is greater of 0,t
WDD
–t
WP
(actual) or t
DDD
–t
DW
(actual).
17. To ensure that the earlier of the two ports wins.
18. To ensure that write cycle is inhibited during contention.
19. To ensure that a write cycle is completed after contention.
20. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with Port-to-port Delay.”
Description
7C133-25
7C143-25
Min.
7C133-35
7C143-35
Min.
7C133-55
7C143-55
Min.
Unit
Max.
Max.
Max.
Read Cycle Time
Address to Data Valid
[10]
Data Hold from Address Change
CE LOW to Data Valid
[10]
OE LOW to Data Valid
[10]
OE LOW to Low Z
[11, 12,13]
OE HIGH to High Z
[11, 12,13]
CE LOW to Low Z
[11, 12,13]
CE HIGH to High Z
[11, 12,13]
CE LOW to Power-Up
[13]
CE HIGH to Power-Down
[13]
25
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
35
55
0
0
0
25
20
35
25
55
30
3
3
3
15
20
25
3
5
5
15
20
20
0
0
0
25
25
25
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
R/W Pulse Width
Data Set-up to Write End
Data Hold from Write End
R/W LOW to High Z
[12,13]
R/W HIGH to Low Z
[12,13]
25
20
20
2
0
20
15
0
35
25
25
2
0
25
20
0
55
40
40
2
0
35
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
20
20
0
0
0
25
20
20
20
50
35
35
30
25
20
60
45
50
40
35
30
80
55
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse to Data Delay
[15]
Write Data Valid to Read Data Valid
[15]
BUSY High to Valid Data
[16]
Arbitration Priority Set Up Time
[17]
Note 16
Note 16
Note 16
5
5
5
Write to BUSY
[18]
Write Hold After BUSY
[19]
Write Pulse to Data Delay
[20]
Write Data Valid to Read Data Valid
[20]
0
0
0
ns
ns
ns
ns
20
25
30
50
35
60
45
80
55
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