- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄298975 > CY7C1612KV18-333BZXC (CYPRESS SEMICONDUCTOR CORP) 8M X 18 QDR SRAM, PBGA165 PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C1612KV18-333BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 8M X 18 QDR SRAM, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 340K |
| 代理商： | CY7C1612KV18-333BZXC |
ADVANCE
INFORMATION
CY7C1610KV18, CY7C1625KV18
CY7C1612KV18, CY7C1614KV18
144-Mbit QDR-II SRAM 2-Word
Burst Architecture
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 001-16238 Rev. **
Revised June 21, 2007
Features
■ Separate independent read and write data ports
Supports concurrent transactions
■ 333 MHz clock for high bandwidth
■ 2-word burst on all accesses
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self timed writes
■ QDR-II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
■ Available in ×8, x9, x18, and x36 configurations
■ Full data coherency providing most current data
■ Core VDD = 1.8V(±0.1V); IO VDDQ = 1.4V to VDD
■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Phase Locked Loop (PLL) for accurate data placement
Configurations
CY7C1610KV18 – 16M x 8
CY7C1625KV18 – 16M x 9
CY7C1612KV18 – 8M x 18
CY7C1614KV18 – 4M x 36
Functional Description
The CY7C1610KV18, CY7C1625KV18, CY7C1612KV18, and
CY7C1614KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture consists
of two separate ports to access the memory array. The read port
has dedicated data outputs to support read operations and the
write port has dedicated data inputs to support write operations.
QDR-II architecture has separate data inputs and data outputs
to completely eliminate the need to turn around the data bus that
exists with common IO devices. Each port is accessed through
a common address bus. The read address is latched on the
rising edge of the K clock and the write address is latched on the
rising edge of the K clock. Accesses to the QDR-II read and write
ports are completely independent of one another. To maximize
data throughput, both read and write ports are equipped with
DDR interfaces. Each address location is associated with two
8-bit words (CY7C1610KV18), 9-bit words (CY7C1625KV18),
18-bit
words
(CY7C1612KV18),
or
36-bit
words
(CY7C1614KV18) that burst sequentially into or out of the
device. Because data is transferred into and out of the device on
every rising edge of input clocks (K and K and C and C), memory
bandwidth is maximized while simplifying system design by
eliminating bus turn arounds.
Port selects for each port enable depth expansion. Port selects
allow each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Parameter
333 MHz
300 MHz
250 MHz
200 MHz
Unit
Maximum Operating Frequency
333
300
250
200
MHz
Maximum Operating Current
x8/x9
850
780
680
580
mA
x18
870
810
700
590
x36
1060
980
850
710
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C256-45PC | 32K X 8 OTPROM, 45 ns, PDIP28 |
| CY7C2561KV18-450BZC | 8M X 8 QDR SRAM, 0.37 ns, PBGA165 |
| CY7C2566KV18-450BZI | 8M X 8 DDR SRAM, 0.37 ns, PBGA165 |
| CY7C293AL-35WC | 2K X 8 UVPROM, 35 ns, CDIP24 |
| CY7C474-15DI | 32K X 9 OTHER FIFO, 15 ns, CDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C16135SCCYP | 制造商:CYP 功能描述:7C161-35 |
| CY7C1613KV18-250BZXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1613KV18-300BZI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 144Mb (8Mx18) QDR II QDR II + 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1613KV18-300BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 CY7C1613KV18-300BZXC RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1613KV18-333BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 CY7C1613KV18-333BZXC RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。