參數(shù)資料
型號(hào)： CY8C24794-SPE
廠商： Cypress Semiconductor Corp.
英文描述： PSoCTM Mixed-Signal Array
中文描述： PSoCTM混合信號(hào)陣列
文件頁數(shù)： 18/32頁
文件大?。?/td> 366K
代理商： CY8C24794-SPE
April 14, 2005
Document No. 38-12018 Rev. *F
18
CY8C24794 Final Data Sheet
3. Electrical Specifications
3.3.6
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 3-11. 5V DC Analog Reference Specifications
Symbol
BG
–
Description
Min
Typ
Max
Units
Bandgap Voltage Reference
AGND = Vdd/2
a
AGND = 2 x BandGap
a
AGND = P2[4] (P2[4] = Vdd/2)
a
AGND = BandGap
a
AGND = 1.6 x BandGap
a
AGND Block to Block Variation (AGND = Vdd/2)
a
RefHi = Vdd/2 + BandGap
1.28
Vdd/2 - 0.04
1.30
Vdd/2 - 0.01
1.32
Vdd/2 + 0.007
V
V
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
–
2 x BG - 0.048
2 x BG - 0.030
2 x BG + 0.024
V
–
P2[4] - 0.011
P2[4]
P2[4] + 0.011
V
–
BG - 0.009
BG + 0.008
BG + 0.016
V
–
1.6 x BG - 0.022
1.6 x BG - 0.010
1.6 x BG + 0.018
V
–
-0.034
0.000
0.034
V
–
Vdd
/2 + BG - 0.10
3 x BG - 0.06
2 x BG + P2[6] - 0.113
P2[4] + BG - 0.130
P2[4] + P2[6] - 0.133
3.2 x BG - 0.112
Vdd
/2 - BG - 0.04
BG - 0.06
2 x BG - P2[6] - 0.084
P2[4] - BG - 0.056
P2[4] - P2[6] - 0.057
Vdd
/2 + BG
3 x BG
2 x BG + P2[6] - 0.018
P2[4] + BG - 0.016
P2[4] + P2[6] - 0.016
3.2 x BG
Vdd
/2 - BG
+
0.024
BG
2 x BG - P2[6] + 0.025
P2[4] - BG + 0.026
P2[4] - P2[6] + 0.026
Vdd
/2 + BG + 0.10
3 x BG + 0.06
2 x BG + P2[6] + 0.077
P2[4] + BG + 0.098
P2[4] + P2[6]+ 0.100
3.2 x BG + 0.076
Vdd
/2 - BG + 0.04
BG + 0.06
2 x BG - P2[6] + 0.134
P2[4] - BG + 0.107
P2[4] - P2[6] + 0.110
V
–
–
–
–
–
–
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 – BandGap
V
V
V
V
V
V
–
–
–
–
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
V
V
V
V
Table 3-12. 3.3V DC Analog Reference Specifications
Symbol
BG
–
Description
Min
Typ
Max
Units
Bandgap Voltage Reference
AGND = Vdd/2
a
AGND = 2 x BandGap
a
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap
a
AGND = 1.6 x BandGap
a
AGND Column to Column Variation (AGND = Vdd/2)
a
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 - BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
1.28
Vdd/2 - 0.03
1.30
Vdd/2 - 0.01
1.32
Vdd/2 + 0.005
V
V
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
–
Not Allowed
–
–
P2[4] - 0.008
BG - 0.009
P2[4] + 0.001
BG + 0.005
P2[4] + 0.009
BG + 0.015
V
V
–
1.6 x BG - 0.027
1.6 x BG - 0.010
1.6 x BG + 0.018
V
–
-0.034
0.000
0.034
V
–
–
–
–
–
–
–
–
–
–
–
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] + P2[6] - 0.075
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] - P2[6] - 0.048
P2[4] + P2[6] - 0.009
P2[4] + P2[6] + 0.057
V
P2[4]- P2[6] + 0.022
P2[4] - P2[6] + 0.092
V
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