
CYNSE70032
Document #: 38-02042 Rev. *E
Page 114 of 126
16.0
Power
16.1
Proper power-up sequence is required to correctly initialize the Cypress Network Search Engines before functional access to the
device can begin. RST_L and TRST_L should be held low before the power supplies ramp-up. RST_L must be set low for a
duration of time afterward and then set high. The following steps describe the proper power-up sequence.
1. Set RST_L and TRST_L low.
2. Power up V
DD
, V
DDQ
and start running CLK2X and PHS_L. The order in which these signals (including V
DD
and V
DDQ
) are
applied is not critical.
3. Hold RST_L low for a minimum of 64 CLK2X cycles. The counting starts on the first rising edge of CLK2X when PHS_L is
high, after both V
DD
and V
DDQ
have reached their steady state voltages. Set RST_L high afterward to complete the power-up
sequence. For JTAG reset, TRST_L can be brought high after both V
DD
and V
DDQ
have reached their steady state voltages.
Figure 16-1
illustrates the proper sequences of the power-up operation
.
The Proper Power-up Sequence
17.0
Application
Figure 17-1
shows how a search engine subsystem can be formed using a host ASIC and Cypress’s CYNSE70032 bank. It also
shows how this search engine subsystem is integrated in a switch or router. The CYNSE70032 can access synchronous as well
as asynchronous SRAMs by allowing the host ASIC to set the same HLAT parameter in the all search engines within a bank of
search engines.
Figure 16-1. Power-up Sequence
VDD
VDDQ
64 CLK2x
cycles
CLK2x
PHS_L
RST_L
TRST_L