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參數(shù)資料
| 型號(hào)： | CYP15G0401DXB-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Quad HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | BGA-256 |
| 文件頁數(shù)： | 25/48頁 |
| 文件大小： | 1115K |
| 代理商： | CYP15G0401DXB-BGI |
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CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 25 of 48
require a framing event before it will correctly decode charac-
ters.
When RXCKSEL is MID (or open), each received channel out-
put register is clocked by the recovered clock for that channel.
Since no characters may be added or deleted, the receiver
Elasticity Buffer is bypassed.
When RXCKSEL = HIGH, all channels are clocked by the se-
lected recovered clock. This selection is made using the
RXCLKB+ and RXCLKD+ signals as inputs per
Table 16
. This
selected clock is always output on RXCLKA
±
and RXCLKC
±
.
In this mode the receive Elasticity Buffers are enabled. When
data is output using a recovered clock (RXCKSEL = HIGH),
receive channels are not allowed to insert and delete charac-
ters, except as necessary for Elasticity Buffer alignment.
Prior to reception of valid data, at least one Word Sync Se-
quence (or that portion of one necessary to align the receive
buffers) must be received to allow the receive Elasticity Buffers
to be centered. The Elasticity buffer may also be set by a de-
vice reset operation initiated through the TRSTZ input, howev-
er, following such an event the CYP15G0401DXA will normally
require a framing event before it will correctly decode charac-
ters. Since the Elasticity buffer is not allowed to insert or delete
framing characters, the transmit clocks on the channels must
all be from a common source.
Dual-Channel Bonded Modes
In dual-channel bonded modes (RX Modes 3 and 5, where
RXMODE[1] = MID or open), the associated receive channel
pair output registers must be clocked by a common clock. This
mode does not operate when RXCKSEL = MID.
Proper operation in this mode requires that the associated
transmit data streams are clocked from a common reference
with no long-term character slippage between the bonded
channels. In dual-channel mode this means that channels A
and B must be clocked from a common reference, and chan-
nels C and D must be clocked from a common reference
(all four transmit channels
may
be clocked from the same
source, but that is not a requirement).
Prior to reception of valid characters, at least one Word Sync
Sequence (or that portion of one necessary to align the receive
buffers) must be received on the bonded channels (within the
allowable inter-channel skew window) to allow the receive
Elasticity Buffers to be centered. While normal characters may
be output prior to this alignment event, they are not necessarily
aligned within the same boundaries that they were transmitted.
When RXCKSEL = LOW, all four receive channels are clocked
by REFCLK. RXCLKB
±
and RXCLKD
±
outputs are disabled
(High-Z), and RXCLKA
±
and RXCLKC
±
present a buffered
and delayed form of REFCLK. In this mode, the receive Elas-
ticity Buffers are enabled. For REFCLK clocking, the Elasticity
Buffers must be able to insert K28.5 characters and delete
framing characters as appropriate. While these insertions and
deletions can take place at any time, they must occur at the
same time on both channels that are bonded together. This is
necessary to keep the data in the bonded channel-pairs prop-
erly aligned. This insert and delete process is controlled by the
channel selected using the RXCLKB+ and RXCLKD+ inputs
using the decodes listed in
Table 17
.
When RXCKSEL = HIGH, the A and B channels are clocked
by the selected recovered clock, and the C and D channels are
clocked by the selected recovered clock, as shown in
Table 17
. The output clock for the channel A/B bonded-pair is
output continuously on RXCLKA
±
. The clock source for this
output is selected from the recovered clock for channel A or
channel B using the RXCLKB+ input. The output clock for the
channel C/D bonded-pair is output continuously on RXCLKC
±
.
The clock source for this output is selected from recovered
clock for channel C or channel D using the RXCLKD+ input.
When data is output using a recovered clock (RXCKSEL =
HIGH), receive channels are not allowed to insert and delete
characters, except as necessary for Elasticity Buffer align-
ment.
Quad Channel Modes
In quad-channel modes (RX modes 6 and 7, where
RXMODE[1] = HIGH), all four receive channel output registers
must be clocked by a common clock. This mode does not op-
erate when RXCKSEL = MID.
Proper operation in this mode requires that the four transmit
data streams are clocked from a common reference with no
long-term character slippage between the bonded channels.
In quad-channel modes this means that the transmit channels
A, B, C, and D must all be clocked from a common reference.
Prior to reception of valid data, at least one Word Sync Se-
quence (or that portion of one necessary to align the receive
buffers) must be received on all four bonded channels (within
the allowable inter-channel skew window) to allow the receive
Elasticity Buffers to be centered and aligned.
When RXCKSEL = LOW, all four receive channels are clocked
by the internal derivative of REFCLK. RXCLKB
±
and
RXCLKD
±
outputs are disabled (High-Z), and RXCLKA
±
and
RXCLKC
±
present a buffered and delayed form of REFCLK.
In this mode the receive Elasticity Buffers are enabled. For
REFCLK clocking, the Elasticity Buffers must be able to insert
K28.5 characters and delete framing characters as appropri-
ate. While these insertions and deletions can take place at any
time, they must occur at the same time on all four channels.
This is necessary to keep the data in the four bonded channels
properly aligned. This insert and delete process is controlled
by the channel selected using the RXCLKB+ and RXCLKD+
inputs using the decode listed in
Table 16
.
Table 16. Independent and Quad Channel Bonded
Recovered Clock Select
RXCLKB+
0
0
1
1
RXCLKD+
0
1
0
1
RXCLKA
±
/RXCLKC
±
Clock Source
RXCLKA
RXCLKB
RXCLKC
RXCLKD
Table 17. Dual-Channel Bonded Recovered Clock Select
RXCLKB+
0
1
X
X
RXCLKD+
X
X
0
1
Clock Source
RXCLKA
±
RXCLKA
RXCLKB
RXCLKC
±
RXCLKC
RXCLKD
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PDF描述 |
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| CYP15G0401DXA-BGC | Quad HOTLink II Transceiver |
| CYP15G0401DXA-BGI | Quad HOTLink II Transceiver |
| CYRF6936 | WirelessUSB LP 2.4GHz Radio SoC(WirelessUSB LP 2.4GHz無線SoC) |
| CYV15G0104TRB | Independent Clock HOTLink II Serializer and Reclocking Deserializer(獨(dú)立時(shí)鐘，HOTLink II并串轉(zhuǎn)換器及時(shí)鐘恢復(fù)串并轉(zhuǎn)換器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0401DXB-BGXC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0401DXB-BGXCKG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0401DXBBGXI | 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0401DXB-BGXI | 功能描述:電信線路管理 IC Quad HOTLink II XCVR Ch 1.5Gbps Backplane RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0401DX-BGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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