參數(shù)資料
型號: DAC1208D750HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
封裝: DAC1208D750HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1208D750HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 21/98頁
文件大?。?/td> 554K
代理商: DAC1208D750HN
DAC1208D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 6 December 2010
21 of 98
NXP Semiconductors
DAC1208D750
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
10.2.6
Frame assembly
DAC1208D750 supports only /F/ = 1, which means that every frame clock period carries
one byte per lane. Frame assembly combines the octet of lane_0 with the four MSB bits of
lane_1 and reassembles the original 12-bit
sample. The same is done for lane_2 and
lane_3. Tail bits are dropped.
The frame assembler also handles previously triggered errors.
If scrambling is enabled:
If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in
lane_0 and/or lane_1, the previous 12-bit sample is repeated twice for I (lane_0,
lane_1). The same is done for Q (lane_2, lane_3).
If scrambling is disabled:
If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in
lane_0 and/or lane_1, the previous 12-bit sample will be repeated once for I (lane_0,
lane_1). The same is done for Q (lane_2, lane_3).
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