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參數(shù)資料
| 型號(hào)： | DAC250Y |
| 英文描述： | Dual, 12-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 雙通道，12位，125Msps數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 5/17頁(yè) |
| 文件大小： | 389K |
| 代理商： | DAC250Y |
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DAC2902
SBAS167A
5
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
S
t
H
t
LPW,
t
CPW
t
CW
Input Setup Time
Input Hold Time
Latch/Clock Pulsewidth
Delay Rising CLK Edge to
Rising WRT Edge
Propagation Delay
Settling Time (0.1%)
2
ns
ns
ns
ns
1.5
3.5
0
4
t
PW
–
2
t
PD
t
SET
1
30
ns
ns
TIMING DIAGRAM
t
PD
t
H
t
LPW
t
CPW
t
CW
t
SET
D[11:0]
(n)
D[11:0]
(n + 1)
t
S
I
OUT(n)
I
OUT(n +1)
50%
DATA IN
WRT1
WRT2
CLK1
CLK2
I
OUT
1
I
OUT
2
DIGITAL INPUTS AND TIMING
The data input ports of the DAC2902 accepts a standard
positive coding with data bit D11 being the most significant
bit (MSB). The converter outputs support a clock rate of up
to 125MSPS. The best performance will typically be achieved
with a symmetric duty cycle for write and clock; however,
the duty cycle may vary as long as the timing specifications
are met. Also, the set-up and hold times may be chosen
within their specified limits.
All digital inputs of the DAC2902 are CMOS compatible.
The logic thresholds depend on the applied digital supply
voltages, such that they are set to approximately half the
supply voltage; V
th
= +V
D
/2 (±20% tolerance). The DAC2902
is designed to operate with a digital supply (+V
D
) of +3.0V
to +5.5V.
The two converter channels within the DAC2902 consist of
two independent, 12-bit, parallel data ports. Each DAC-
channel is controlled by its own set of write (WRT1, WRT2)
and clock (CLK1, CLK2) inputs. Here, the WRT lines
control the channel input latches and the CLK lines control
the DAC latches. The data is first loaded into the input latch
by a rising edge of the WRT line. This data is presented to
the DAC latch on the following falling edge of the WRT
signal. On the next rising edge of the CLK line, the DAC is
updated with the new data and the analog output signal will
change accordingly. The double latch architecture of the
DAC2902 results in a defined sequence for the WRT and
CLK signals, expressed by parameter ‘t
CW
’. A correct tim-
ing is observed when the rising edge of CLK occurs at the
same time, or before, the rising edge of the WRT signal. This
condition can simply be met by connecting the WRT and
CLK lines together. Note that all specifications were mea-
sured with the WRT and CLK lines connected together.
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| DAC2902Y | Dual, 12-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER |
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| DAC2902 | Dual, 12-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| DAC2534-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| DAC2534-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| DAC259K59B WAF | 制造商:ON Semiconductor 功能描述: |
| DAC2800D | 制造商:MSK 制造商全稱:M.S. Kennedy Corporation 功能描述:6W DUAL DC - DC CONVERTERS |
| DAC2800S | 制造商:MSK 制造商全稱:M.S. Kennedy Corporation 功能描述:5.4W DC-DC CONVERTERS |
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