參數(shù)資料
型號(hào)： DAC2932PFBT
元件分類(lèi)： DAC
英文描述： DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER
中文描述： 雙通道12位40MSPS數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 20/24頁(yè)
文件大?。?/td> 343K
代理商： DAC2932PFBT
SBAS279C AUGUST 2003 REVISED OCTOBER 2004
www.ti.com
20
Alternatively, bringing GSET low (that is, connected to
AGND), switches the DAC2932 into the simultaneous gain
set mode. Now the full-scale output current of both DAC
channels is determined by only one external R
SET
resistor
connected to the FSA1 pin. The resistor at the FSA2 pin
may be removed; however, this is not required since this
pin is not functional in this mode and the resistor has no
effect on the gain equation. The formula for deriving the
correct R
SET
remains unchanged. For example,
R
SET
= 19.6k
will result in a 2mA output for both DACs.
The DAC2932 is specified with GSET being high and
operating in inpendent gain mode. It should be noted that
when using the simultaneous gain mode, the gain error
and gain matching error will increase.
EXTERNAL REFERENCE OPERATION
The internal reference can be disabled by simply applying
an external reference voltage into the REF
IN
pin, which in
this case functions as an input, as shown in Figure 37. The
use of an external reference may be considered for
applications that require higher accuracy and drift
performance.
R
SET
External
Reference
I
REF
=V
REF
R
SET
DAC2932
+1.22VRef.
FSA
+3V
+V
A
REF
IN
Current
Sources
Ref
Control
Amp
Figure 37. External Reference Configuration
While a 0.1
μ
F capacitor is recommended for use with the
internal reference, it is optional for the external reference
operation. The reference input, REF
IN
, has a high input
impedance and can easily be driven by various sources.
VDAC
The architecture consists of a resistor string DAC followed
by an output buffer amplifier. Figure 38 shows a block
diagram of the DAC architecture.
DAC Register
REF (+)
Resistor
String
REF(
)
Output
Amplifier
GND
REFV
(+V
DV
)
V
OUT
Figure 38. V-DAC Architecture
The input coding to the V-DAC is straight binary, so the
ideal output voltage is given by:
V
OUT
REFV
D
4096
where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 4095.
SERIAL INTERFACE
The VDACs have a three-wire serial interface (SYNC,
SCLK, and DIN), which is compatible with SPI, QSPI, and
Microwire interface standards as well as most Digital
Signal Processors (DSPs).
The write sequence begins by bringing the SYNC line low.
Data from the DIN line is clocked into the 16-bit shift
register on the falling edge of SCLK. The serial clock
frequency can be as high as 20MHz, making the V-DACs
compatible with high-speed DSPs. On the 16th falling
edge of the serial clock, the last data bit is clocked in and
the programmed function is executed (that is, a change in
DAC register contents and/or a change in the mode of
operation).
At this point, the SYNC line may be kept low or brought
high. In either case, it must be brought high for a minimum
of 50ns before the next write sequence so that a falling
edge of SYNC can initiate the next write sequence. Since
the SYNC buffer draws more current when the SYNC
signal is high than it does when it is low, SYNC should be
idled low between write sequences for lowest power
operation of the part. As mentioned above, however, it
must be brought high again just before the next write
sequence.
(11)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DAC2932PFBTG4 功能描述:數(shù)模轉(zhuǎn)換器- DAC Dual 12-Bit 40MSPS RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC-2-CG 制造商:Thomas & Betts 功能描述:
DAC2K5G4 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:20-Bit, Low-Power Digital-to-Analog Converter
DAC2KY 制造商:BB 制造商全稱(chēng):BB 功能描述:Dual, 12-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER
DAC312 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:12-Bit High Speed Multiplying D/A Converter
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