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參數(shù)資料
| 型號： | DAC2932PFBTG4 |
| 元件分類： | DAC |
| 英文描述： | DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER |
| 中文描述： | 雙通道12位40MSPS數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 343K |
| 代理商： | DAC2932PFBTG4 |
SBAS279C AUGUST 2003 REVISED OCTOBER 2004
www.ti.com
3
ELECTRICAL CHARACTERISTICS: I-DAC
At TA = TMIN to TMAX (typical values are at TA = 25
°
C), +VA = +3V, +VD = +3V, Update Rate = 40MSPS, IOUTFS = 2mA, RL = 250
, CL
≤
10pF,
GSET = H, and internal reference, unless otherwise noted.
DAC2932
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
Resolution
Output update rate (fCLOCK)
Specified temperature range, operating
Static Accuracy(1)(2)
Differential nonlinearity (DNL)
Integral nonlinearity (INL)
Dynamic Performance(3)
Spurious-free dynamic range (SFDR)
fOUT = 0.2MHz, fCLOCK = 20MSPS
fOUT = 0.55MHz, fCLOCK = 40MSPS
fOUT = 1MHz, fCLOCK = 25MSPS(4)
fOUT = 2.2MHz, fCLOCK = 40MSPS
fOUT = 5MHz, fCLOCK = 40MSPS
fOUT = 10MHz, fCLOCK = 40MSPS
fOUT = 20MHz, fCLOCK = 40MSPS
Spurious-free dynamic range within a
window
fOUT = 2.2MHz, fCLOCK = 40MSPS
fOUT = 10MHz, fCLOCK = 40MSPS
Total harmonic distortion (THD)
fOUT = 0.55MHz, fCLOCK = 40MSPS
fOUT = 1MHz, fCLOCK = 25MSPS(4)
fOUT = 2.2MHz, fCLOCK = 40MSPS
Signal-to-noise and distortion (SINAD)
fOUT = 1MHz, fCLOCK = 25MSPS(4)
Output settling time(1)
Output rise time(1)
Output fall time(1)
DC Accuracy
Full-scale output range(5)(6) (FSR)
Output compliance range(7), VCO
Gain error (Full-Scale)
Gain error drift
Gain matching
Offset error
Power-supply rejection, +VA
Power-supply rejection, +VD
Output resistance
Output capacitance
12
40
Bits
MSPS
°
C
Ambient, TA
40
+85
3.5
8
±
0.5
±
1.5
+3.5
+8
LSB
LSB
To Nyquist, 0dBFS
68
71
70
72
75
69
57
dBc
dBc
dBc
dBc
dBc
dBc
dBc
58
1MHz span
2MHz span
76
74
dBc
dBc
70
69
70
dBc
dBc
dBc
58
52
61
20
7.7
7.4
dBc
ns
ns
ns
to 0.1%
10% to 90%
10% to 90%
All bits high, IOUT1, IOUT2
0.5
0.5
2
2
mA
V
%FSR
ppmFSR/
°
C
%FSR
%FSR
%FSR/V
%FSR/V
k
pF
+0.5
±
0.5
70
+0.6
±
0.001
+0.5
+0.03
200
5
+0.8
+2
2.5
+2.5
+3V,
±
10%, at 25
°
C
+3V,
±
10%, at 25
°
C
0.9
0.12
+0.9
+0.12
IOUT, IOUT to Ground
(1)At output IOUT1, IOUT2, while driving a 250
load, transition from 000h to FFFh.
(2)Measured at fCLOCK = 25MSPS and fOUT = 1.0MHz.
(3)Differential, transformer (n = 4:1) coupled output, RL = 400
.
(4)Differential outputs with a 250
load.
(5)
Nominal fullscale output current is I
OUTFS
(6)Ensured by design and characterization; not production tested.
(7)Gain error to remain
≤
10% FSR over the full compliance range.
(8)Combined power dissipation of I-DAC and V-DAC.
32
I
REF
32
V
REF
R
SET
; with V
REF
1.22V (typ) and R
SET
19.6k
(1%)
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