參數(shù)資料
型號(hào)： DAC2932PFBTG4
元件分類： DAC
英文描述： DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER
中文描述： 雙通道12位40MSPS數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 7/24頁(yè)
文件大?。?/td> 343K
代理商： DAC2932PFBTG4
SBAS279C AUGUST 2003 REVISED OCTOBER 2004
www.ti.com
7
SCLK
DB15
DB0
SYNC
DIN
t
1
t
2
t
7
t
3
t
4
t
8
t
5
t
6
Figure 2. Serial Write Operation of V-DAC
TIMING REQUIREMENTS
(1,2)
: V-DAC
PARAMETER
DESCRIPTION
t1(3)
SCLK cycle time
t2
SCLK high time
t3
SCLK low time
t4
SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
SCLK falling edge to SYNC rising edge
t8
Minimum SYNC high time
PDV fall time to VOUT (V-DAC coming out of power-down mode)
(1)All input signals are specified with tr = tf
≤
2ns (10% to 90% of +VDV) and timed from a voltage level of (VIL + VIH)/2.
(2)Based on design simulation and characterization; not production tested.
(3)Maximum SCLK frequency is 20MHz at +VAV = +VDV = +2.7V to 3.3V.
MIN
50
TYP
MAX
UNIT
ns
13
ns
22.5
ns
0
ns
5
7.5
ns
1.5
2.5
ns
0
6.0
ns
50
ns
μ
s
8
VDAC: SERIAL DATA INPUT FORMAT
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
A0
DAC1
A1
DAC2
A2
DAC3
A3
DAC4
D11
(MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
Address Bits
12-Bit Data Word
NOTE: A logic high in the address bit will select the corresponding V-DAC and write the data word into its register. If more than one address bit
is set high, the selected V-DACs are updated with the same data word simultaneously.
相關(guān)PDF資料
PDF描述
DAC2932 DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER
DAC2932PFBR DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER
DAC2932PFBT DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER
DAC312BR 12-Bit Digital-to-Analog Converter
DAC312GBC 12-Bit Digital-to-Analog Converter
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DAC312BR 制造商:Rochester Electronics LLC 功能描述:12-BIT HIGH-SPEED MULTIPL - Bulk
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