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參數(shù)資料
| 型號(hào)： | DAC312HSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT MULT HS 20SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 250ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 375mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | * |
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DAC312
–13–
REV. C
DESCRIPTION OF OPERATION
The DAC312 is divided into two major sections, an 8 segment
generator and a 9-bit master/slave D/A converter. In operation
the device performs as follows (see Simplified Schematic).
The three most significant bits (MSBs) are inputs to a 3-to-8
line decoder. The selected resistor (R5 in the figure) is con-
nected to the master/slave 9-bit D/A converter. All lower order
resistors (R1 through R4) are summed into the IO line, while all
higher order resistors (R6 through R8) are summed into the IO
line. The R5 current supplies 512 steps of current (0 mA to
0.499 mA for a 1 mA reference current) which are also summed
into the IO or IO lines depending on the bits selected. In the fig-
ure, the code selected is: 100 110000000. Therefore, 2 mA (4
×
0.5 mA/segment) +0.375 mA (from master/slave D/A converter)
are summed into IO giving an IO of 2.375 mA. IO has a current
of 1.625 mA with this code. As the three MSB’s are increment-
ed, each successively higher code adds 0.5 mA to IO and sub-
tracts 0.5 mA from IO, with the selected resistor feeding its
current to the master/slave D/A converter; thus each increment
of the 3 MSBs allows the current in the 9-bit D/A converter to
be added to a pedestal consisting of the sum of all lower order
currents from the segment generator. This configuration guar-
antees monotonicity.
Expanded Transfer Characteristic Segment (001 010 011)
Simplified Schematic
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