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參數(shù)資料
| 型號(hào)： | DAC4815AP |
| 英文描述： | Quad 12-Bit Digital-to-Analog Converter 8-Bit Port Interface |
| 中文描述： | 四路12位數(shù)字到模擬轉(zhuǎn)換器8位端口接口 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大小： | 179K |
| 代理商： | DAC4815AP |
7
DAC4815
PARAMETER
MINIMUM
t
1
—Address Valid to Write Setup Time
t
2
—Address Valid to Write Hold Time
t
3
—Data Setup Time
t
4
—Data Hold Time
t
—Chip Select to LE or Write
Setup Time
t
6
—Chip Select to LE or Write
Hold Time
t
7
—Write Pulse Width
t
8
—Clear Pulse Width
20ns
10ns
30ns
10ns
0ns
0ns
40ns
40ns
TIMING CHARACTERISTICS
+V
L
= +5V, T
A
= –40
°
C to +85
°
C.
NOTE: X = Don’t care.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1
LSB change in the output voltage when the input code
changes by 1 LSB. A differential nonlinearity specification
of
±
1 LSB maximum guarantees monotonicity.
BIPOLAR ZERO ERROR
The output voltage for code 800
HEX
.
GAIN ERROR
The deviation of the output voltage span (V
MAX
– V
MIN
)
from the ideal span of 20V – 1 LSB (bipolar mode). The gain
error is specified with and without the internal +10V refer-
ence error included.
OUTPUT SETTLING TIME
The time required for the output voltage to settle within a
percentage-of-full-scale error band for a full scale transition.
Settling to
±
0.012% (1/2 LSB) is specified for the DAC4815.
DISCUSSION OF
SPECIFICATIONS
INPUT CODES
All digital inputs of the DAC4815 are TTL and 5V CMOS
compatible. Input codes for the DAC4815 are BOB (Bipolar
Offset Binary). See Figure 3 for
±
10V bipolar connection.
INTEGRAL OR RELATIVE LINEARITY
This term, also know as end point linearity, describes the
transfer function of analog output to digital input code.
Integral linearity error is the deviation of the analog output
versus code transfer function from a straight line drawn
through the end points.
BIPOLAR OUTPUTS FOR SELECTED INPUT
DIGITAL INPUT
BIPOLAR (BOB)
FFF
HEX
800
HEX
7FF
HEX
000
HEX
+Full Scale
Zero
Zero – 1 LSB
–Full Scale
t
5
t
6
t
7
t
8
CS
LE, WR
CLR
0V
5V
0V
5V
0V
5V
0V
5V
0V
NOTES: (1) All input signal rise and fall times are measured
from 10% to 90% of +5V. t = t = 5ns.
(2) Timing measurement reference level is V + V .
2
t
1
t
3
t
4
t
2
5V
DATA
A
0
-A
2
INTERFACE LOGIC TRUTH TABLE
CLR
LE
CS
WR
A
2
0
0
0
0
1
1
1
1
X
X
X
X
X
A
1
0
0
1
1
0
0
1
1
X
X
X
X
X
A
0
0
1
0
1
0
1
0
1
X
X
X
X
X
FUNCTION
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
X
1
X
0
0
0
0
0
0
0
0
0
0
1
X
X
0
0
0
0
0
0
0
0
1
0
X
1
X
DAC A LS input register loaded with D7-D0(LSB)
DAC A MS input register loaded with D3(MSB)-D0
DAC B LS input register loaded with D7-D0(LSB)
DAC B MS input register loaded with D3(MSB)-D0
DAC C LS input register loaded with D7-D0(LSB)
DAC C MS input register loaded with D3(MSB)-D0
DAC D LS input register loaded with D7-D0(LSB)
DAC D MS input register loaded with D3(MSB)-D0
All DAC registers updated simultaneously from input registers
All DAC registers are transparent
No data transfer
No data transfer
Input registers cleared = 000
HEX
, DAC registers = 800
HEX
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