參數(shù)資料
型號(hào): DAC5674IPHP
廠商: Texas Instruments
文件頁(yè)數(shù): 13/39頁(yè)
文件大?。?/td> 0K
描述: IC DAC 14BIT 400MSPS 48-HTQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 250
系列: CommsDAC™
設(shè)置時(shí)間: 20ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 550mW
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 48-HTQFP(7x7)
包裝: 托盤(pán)
輸出數(shù)目和類(lèi)型: 2 電流,單極
采樣率(每秒): 400M
產(chǎn)品目錄頁(yè)面: 898 (CN2011-ZH PDF)
配用: 296-30860-ND - EVAL MODULE FOR DAC5674
其它名稱(chēng): 296-15726
296-15726-1
296-15726-1-ND
296-15726-5
296-15726-5-ND
DAC5674
SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005
www.ti.com
20
PLLVDD
PLLGND
CLKGND
CLKVDD
CLK
CLKC
PFD
VCO
/1
/2
/4
/8
/2
D[13:0]
DIV[1:0]
PLLVDD
X4
PLLVDD
PLLLOCK
LPF
s
1
0
Clk
Buffer
Clk_4
y
DAC5674
Charge
Pump
s
1
0
Clk_2
y
Clk_1
y
Data
Figure 21. Clock Generation Functional Diagram
Table 4. Clock Mode Configuration
CLOCK MODE
PLLVDD
DIV[1:0]
X4
DATA RANGE (MHz)
PLLLOCK PIN FUNCTION
External 2
×
0 V
XX
0
DC to 200
External clock/2
External 4
×
0 V
XX
1
DC to 100
External clock/4
Internal 2
×
3.3 V
00
0
100 to 200
Internal PLL lock indicator
Internal 2
×
3.3 V
01
0
50 to 100
Internal PLL lock indicator
Internal 2
×
3.3 V
10
0
25 to 50
Internal PLL lock indicator
Internal 2
×
3.3 V
11
0
12 to 25
Internal PLL lock indicator
Internal 4
×
3.3 V
00
1
50 to 100
Internal PLL lock indicator
Internal 4
×
3.3 V
01
1
25 to 50
Internal PLL lock indicator
Internal 4
×
3.3 V
10
1
12 to 25
Internal PLL lock indicator
Internal 4
×
3.3 V
11
1
5 to 12
Internal PLL lock indicator
Low-Pass Filter
The PLL consists of a type four phase-frequency detector (PFD), charge pump, external low-pass loop filter,
voltage to current converter, and current controlled oscillator (ICO) as shown in Figure 22. The DAC5674
evaluation board comes with component values R = 200, C1 = 0.01
F, and C2 = 100 pF. These values have
been designed to give the phase margins and loop bandwidths listed in Table 5 for the five divide down factors
of prescaling and interpolation. Note that the values derived were based on a charge pump current output of
1 mA and a VCO gain of 300 MHz/V (nominal at Fvco = 400 MHz). With this filter, the settling time from a phase
or frequency disturbance is about 2.5
s. If different PLL dynamics are required, DAC5674 users can design
a second order filter for their application; see the Designing the PLL Loop Filter section of this data sheet.
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