參數(shù)資料
型號： DAC600
英文描述： 12-Bit 256MHz Monolithic DIGITAL-TO-ANALOG CONVERTER
中文描述： 12位256MHz單片數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù)： 2/12頁
文件大?。?/td> 155K
代理商： DAC600
DAC600
2
6
Same as specification for DAC600AN.
NOTES: (1) Linearity tests are measured into a virtual ground (op amp). (2) Gain error in % is calculated by: GE (%) =
(3) Settling time is influenced by the load due to fast edge speeds. Use good transmission line techniques
for best results. (4) Spurious free dynamic range is measured from the fundamental frequency to any harmonic or non-harmonic spurs within the bandwidth f
CLK
/2
C
,
unless otherwise specified.
SPECIFICATIONS
ELECTRICAL
At +25
°
C V
REF
= +1.0V, V
EEA
= V
EED
= –5.2V, unless otherwise noted.
DAC600AN
TYP
DAC600BN
TYP
PARAMETER
DIGITAL INPUTS
Logic
Resolution
ECL Logic Input Levels: V
IL
CONDITIONS
TEMP
MIN
MAX
MIN
MAX
UNITS
12 Parallel Input Lines, ECL
12
–2
2
0
200
6
6
6
6
6
Bits
V
μ
A
V
μ
A
Logic “0”
Full
Full
Full
Full
–1.48
–1.95
6
6
I
IL
V
IH
I
IH
Logic “1”
–1.1
–0.75
6
6
DIGITAL TIMING
Input Data Rate
CLK Pulse Width High or Low
Set-up Time
Hold Time (Referred to CLK)
Propagation Delay
ANALOG OUTPUT
Bipolar Output Current
Output Resistance
Output Capacitance
CONTROL AMPLIFIER
Input Resistance
Full Power Bandwidth
Offset
Input Reference Range
TRANSFER CHARACTERISTICS
Integral Linearity Error
(1)
: V
OUT NOT
Full
Full
Full
Full
Full
DC
1.95
1.5
1.9
256
6
6
6
6
6
MHz
ns
ns
ns
ns
1.0
1.7
2
6
6
6
R
L
= 0
Full
Full
Full
19
47.5
20
50
15
21
52.5
6
49
6
6
6
6
51
mA
pF
Full
Full
+25
°
C
Full
800
10
0
6
6
0
–3dB
MHz
mV
V
±
1
±
0.5
6
100mV
±
1.25
6
Best Fit Straight Line
+25
°
C
Full
+25
°
C
+25
°
C
Full
+25
°
C
+25
°
C
Full
+25
°
C
Full
+25
°
C
Full
+25
°
C
±
0.012
±
0.024
±
0.024
±
0.036
±
0.1
±
0.024
±
0.036
±
0.1%
±
0.006
±
0.012
±
0.012
±
0.024
±
0.1
±
0.012
±
0.024
±
0.1%
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
V
OUT NOT
V
OUT
Differential Linearity Error
(1)
OUT NOT
V
OUT NOT
V
OUT
12-Bit Monotonicity
Guaranteed
Typical
75
57
±
0.5
±
1.3
10
Guaranteed
Guaranteed
50
50
±
0.5
±
1.1
5
Output Offset Current: V
OUT NOT
Bits 1-12 HIGH
150
150
±
1.5
±
2.0
75
100
100
±
1.0
±
2.0
50
μ
A
μ
A
%
%
μ
A
V
OUT NOT
Gain Error
(2)
Output Leakage Current
TIME DOMAIN PERFORMANCE
Glitch Energy
Fall Time
Rise Time
Settling Time
(3)
±
0.1% FSR
±
0.024% FSR
DYNAMIC PERFORMANCE
Spurious Free Dynamic Range
(4)
f
O
= 1MHz
f
O
= 10MHz
f
O
= 1MHz
f
O
= 10MHz
f
O
= 20MHz
f
O
= 10MHz
f
O
= 20MHz
f
= 50MHz
Output Noise
POWER SUPPLIES
Supply Voltages: V
EE
Supply Currents: I
EEA
V
REF
= 0V, Bits 1-12 LOW, V
OUT NOT
Major Carry
90% to 10%
10% to 90%
+25
°
C
+25
°
C
+25
°
C
5.6
510
770
6
6
6
pVs
ps
ps
Major Carry, 1 LSB Change
Full
Full
4
6
6
ns
ns
15
f
CLOCK
= 50MHz
f
CLOCK
= 50MHz
f
CLOCK
= 100MHz
f
CLOCK
= 100MHz
f
CLOCK
= 100MHz
f
CLOCK
= 200MHz
f
CLOCK
= 200MHz
f
CLOCK
= 200MHz
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
74
71
72
68
61
66
58
52
10.6
70
64
70
66
58
66
62
50
77
73
75
70
62
70
67
55
6
dBFS
(3)
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
nV/
√
Hz
Full
Full
Full
Full
–4.5
30
110
–5.2
46
150
900mW
–5.5
60
190
1.3
6
6
6
6
6
6
6
6
6
6
6
V
Pins 33 and 34
Pins 5 and 55
Operating
mA
mA
W
I
EED
Power Consumption
TEMPERATURE RANGE
Specification: DAC600AN, BN
θ
JA
Ambient
Full
–40
+85
6
6
°
C
30
6
°
C/W
V
MEASURED
(FS) –V
IDEAL
(FS)
X
100
V
IDEAL
(FS)
相關(guān)PDF資料
PDF描述
DAC600 12-Bit 256MHz Monolithic Dightal-To-Analog Converter(12位 256MHz單片D/A轉(zhuǎn)換器)
DAC650 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER
DAC650JL 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER
DAC650KL 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER
DAC650 12-Bit 500MHz Dightal-To-Analog Converter(12位 500M赫茲單片D/A轉(zhuǎn)換器)
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