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參數(shù)資料
| 型號(hào)： | DAC667 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大小： | 218K |
| 代理商： | DAC667 |
DAC667
8
Right-justified data can also be accommodated as shown in
Figure 11. The DAC667 still occupies two adjacent loca-
tions in the processor’s memory map. Location X01 loads
the eight LSBs and location X10 loads the four MSBs and
updates the output.
12- AND 16-BIT BUS INTERFACES
For operation with 12- and 16-bit buses, all four address
lines (A0 through A3) are connected to logic 0, and the latch
is enabled by CS asserted low. The DAC667 thus occupies
a single memory location.
This configuration uses the first and second rank registers
simultaneously. The CS input can be driven from an active-
low decoded address. It should be noted that any data bus
activity during the period when CS is low will cause activity
at the DAC667 output. If data is not guaranteed stable during
this period, the second rank register can be used to provide
double buffering. See Figure 12.
OUTPUT
RANGE
DIGITAL
INPUT CODES
CONNECT
PIN 9 TO
CONNECT
PIN 1 TO
CONNECT
PIN 2 TO
CONNECT PIN 4 TO
±
10V
±
5V
±
2.5V
0 to +10V
0 to +5V
Offset Binary
Offset Binary
Offset Binary
Straight Binary
Straight Binary
1
9
NC
6 (Through 50
fixed or 100
trim resistor.)
6 (Through 50
fixed or 100
trim resistor.)
6 (Through 50
fixed or 100
trim resistor.)
5 (Or optional trim. See Figure 7.)
5 (Or optional trim. See Figure 7.)
1 and 2
2
1 and 2
2
2 and 9
3
2 and 9
3
1 and 9
9
1 and 9
9
TABLE III. Output Voltage Range Connections.
FIGURE 10. Left-Justified 8-Bit Bus Interface.
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
D7
D6
D5
D4
D3
D2
D1
D0
WR
DAC667
Address
Decoder
A15
CS
A0
A1
A2
A3
A2
A1
A0
Whenever a 12-bit D/A is loaded from an 8-bit bus, two
bytes are required. If the software program considers the
data to be a 12-bit binary fraction (between 0 and 4095/
4096), the data is left-justified, with the eight most signifi-
cant bits in one byte and the remaining bits in the upper half
of another byte. Right-justified data calls for the eight least
significant bits to occupy one byte, with the four most
significant bits residing in the lower half of another byte,
simplifying integer arithmetic.
Figure 10 shows an addressing scheme for use with a DAC-
667 set up for left-justified data in an 8-bit system. The base
address is decoded from the high-order address bits and the
resultant active-low signal is applied to CS. The two LSBs
of the address bus are connected as shown to the DAC667
address inputs. The latches now reside in two consecutive
locations, with location X01 loading the four LSBs and
location X10 loading the eight MSBs and updating the output.
FIGURE 9. 12-Bit Data Formats for 8-Bit Systems.
DB7
(b) Right-Justified
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
X
X
X
DB11
DB10
DB9
DB8
DB3
(a) Left-Justified
DB2
DB1
DB0
X
X
X
X
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC667AH | 制造商:BURR-BROWN 功能描述: |
| DAC667BH | 制造商:BB 功能描述:_ |
| DAC667JP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| DAC667KP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:BURR-BROWN 功能描述: 制造商:Texas Instruments 功能描述: |
| DAC-6-CG | 制造商:Thomas & Betts 功能描述:2" RIGID TF CONDUIT BODY 制造商:Thomas & Betts 功能描述:Universal Recessed Box And Cover |
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