參數(shù)資料
型號: DAC7612
英文描述: Dual, 12-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER
中文描述: 雙通道,12位串行輸入數(shù)字至模擬轉(zhuǎn)換器
文件頁數(shù): 5/12頁
文件大?。?/td> 126K
代理商: DAC7612
5
DAC7612
TIMING DIAGRAMS
LOGIC TRUTH TABLE
TIMING SPECIFICATIONS
T
A
= –40
°
C to +85
°
C and V
DD
= +5V.
SYMBOL
DESCRIPTION
MIN
TYP
MAX UNITS
t
CH
t
CL
t
LDW
t
DS
t
DH
t
LD1
t
LD2
t
CSS
t
CSH
Clock Width HIGH
30
ns
Clock Width LOW
30
ns
Load Pulse Width
20
ns
Data Setup
15
ns
Data Hold
15
ns
Load Setup
15
ns
Load Hold
10
ns
Select
30
ns
Deselect
20
ns
NOTE: All input control signals are specified with t
R
= t
F
= 5ns (10% to 90%
of +5V) and timed from a voltage level of 2.5V. These parameters are
guaranteed by design and are not subject to production testing.
SDI
CLK
t
CL
t
CH
t
DH
t
DS
SERIAL SHIFT
REGISTER
DAC
DAC
A1
A0
CLK
CS
LOADDACS
REGISTER A
REGISTER B
X
X
L
X
X
X
X
X
H
L
H
H
L
No Change
Shifts One Bit
No Change
No Change
No Change
Loads Serial
Data Word
Loads Serial
Data Word
No Change
No Change
No Change
Loads Serial
Data Word
No Change
H
(1)
H
L
X
H
L
No Change
H
H
X
H
L
No Change
Loads Serial
Data Word
Positive Logic Transition; X = Don’t Care.
NOTE: (1) A HIGH value is suggested in order to avoid to “false clock” from
advancing the shift register and changing the DAC voltage.
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11 B12 B13
A1
A0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA INPUT TABLE
A1
(MSB)
(LSB)
SDI
CLK
CS
LOADDACS
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
CSS
t
LD1
t
LD2
t
CSH
LOADDACS
FS
ZS
V
OUT
t
LDW
t
S
±
1 LSB
Error Band
相關(guān)PDF資料
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