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參數(shù)資料
| 型號： | DAC7625P |
| 元件分類： | 外設及接口 |
| 英文描述： | Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C |
| 中文描述： | 電可擦除可編程邏輯器件 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 311K |
| 代理商： | DAC7625P |
10
DAC7624/7625
ANALOG OUTPUTS
When V
SS
= –5V (dual supply operation), the output ampli-
fier can swing to within 2.25V of the supply rails, guaran-
teed over the –40
°
C to +85
°
C temperature range. With V
SS
= 0V (single-supply operation), the output can swing to
ground. Note that the settling time of the output op-amp will
be longer with voltages very near ground. Also, care must be
taken when measuring the zero-scale error when V
SS
= 0V.
Since the output voltage cannot swing below ground, the
output voltage may not change for the first few digital input
codes (000
H
, 001
H
, 002
H
, etc.) if the output amplifier has a
negative offset.
The behavior of the output amplifier can be critical in some
applications. Under short circuit conditions (DAC output
shorted to ground), the output amplifier can sink a great deal
more current than it can source. See the specification table
for more details concerning short circuit current.
REFERENCE INPUTS
The reference inputs, V
REFL
and V
REFH
, can be any voltage
between V
SS
+2.25V and V
DD
–2.25V provided that V
REFH
is
at least 1.25V greater than V
REFL
. The minimum output of
each DAC is equal to V
REFL
plus a small offset voltage
(essentially, the offset of the output op-amp). The maximum
output is equal to V
REFH
plus a similar offset voltage. Note
that V
SS
(the negative power supply) must either be
connected to ground or must be in the range of –4.75V to
–5.25V. The voltage on V
SS
sets several bias points within
the converter, if V
SS
is not in one of these two configura-
tions, the bias values may be in error and proper operation
of the device is not guaranteed.
The current into the V
REFH
input depends on the DAC output
voltages and can vary from a few microamps to approxi-
mately 0.5 milliamp. The V
REFH
source will not be required
to sink current, only source it. Bypassing the reference
voltage or voltages with at least a 0.1uF capacitor placed as
close to the DAC7624/25 package is strongly recommended.
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7624/25.
Note that each internal register is level triggered and not
edge triggered. When the appropriate signal is LOW, the
register becomes transparent. When this signal is returned
HIGH, the digital word currently in the register is latched.
The first set of registers (the Input Registers) are triggered
via the A0, A1, R/W, and CS inputs. Only one of these
registers is transparent at any given time. The second set of
registers (the DAC Registers) are all transparent when LDAC
input is pulled LOW.
Each DAC can be updated independently by writing to the
appropriate Input Register and then updating the DAC
Register. Alternatively, the entire DAC Register set can be
configured as always transparent by keeping LDAC LOW—
the DAC update will occur when the Input Register is
written.
The double buffered architecture is mainly designed so that
each DAC Input Register can be written at any time and then
all DAC voltages updated simultaneously by pulling LDAC
LOW. It also allows a DAC Input Register to be written to
at any point and the DAC voltage to be synchronously
changed via a trigger signal connected to LDAC.
STATE OF
SELECTED
INPUT
REGISTER
SELECTED
INPUT
REGISTER
STATE OF
ALL DAC
REGISTERS
A1
A0
R/W
CS
RESET
LDAC
L
(1)
L
H
H
L
L
H
H
L
L
H
H
X
(3)
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
X
H
(2)
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
X
A
B
C
D
A
B
C
D
A
B
C
D
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Readback
Readback
Readback
Readback
(All Latched)
(All Latched)
Reset
(4)
Transparent
Transparent
Transparent
Transparent
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Reset
(4)
NONE
NONE
ALL
NOTES: (1) L = Logic LOW. (2) H= Logic HIGH. (3) X = Don’t Care. (4) DAC7624 resets to 800
H
, DAC7625 resets to 000
H
. When RESET rises, all registers that
are in their latched state retain the reset value.
TABLE I. DAC7624 and DAC7625 Control Logic Truth Table.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC7625P | 制造商:BURR-BROWN 功能描述:IC 12BIT DAC 7625 DIP28 |
| DAC7625PB | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit Quad Voltage Output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7625PBG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12B Quad Vltg Output DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7625PG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit Quad Voltage Output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7625U | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit Quad Voltage Output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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