參數(shù)資料
型號: DAC7625P
元件分類: 外設(shè)及接口
英文描述: Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C
中文描述: 電可擦除可編程邏輯器件
文件頁數(shù): 11/11頁
文件大小: 311K
代理商: DAC7625P
11
DAC7624/7625
DIGITAL TIMING
Figure 3 and Table II provide detailed timing for the digital
interface of the DAC7624 and DAC7625.
DIGITAL INPUT CODING
The DAC7624 and DAC7625 input data is in straight binary
format. The output voltage is given by the following equa-
tion:
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
V
OUT
=
V
REFL
+
V
REFH
– V
REFL
4096
(
)
N
t
RCS
CS
t
RDS
t
RDH
t
AS
t
CSD
t
DZ
t
AH
R/W
A0/A1
Data Out
Data Valid
t
WCS
CS
t
WS
t
AS
t
AH
t
WH
R/W
A0/A1
t
RESET
t
LWD
t
LH
LDAC
t
DS
t
DH
t
LS
Data In
RESET
Data Output Timing
Digital Input Timing
FIGURE 3. Digital Input and Output Timing.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
RCS
t
RDS
t
RDH
DZ
t
CSD
t
WCS
t
WS
t
WH
t
AS
t
AH
t
LS
t
LH
t
DS
t
DH
t
LWD
t
RESET
CS LOW for Read
R/W HIGH to CS LOW
R/W HIGH after CS HIGH
CS HIGH to Data Bus in High Impedance
CS LOW to Data Bus Valid
CS LOW for Write
R/W LOW to CS LOW
R/W LOW after CS HIGH
Address Valid to CS LOW
Address Valid after CS HIGH
LDAC LOW to CS LOW
LDAC LOW after CS HIGH
Data Valid to CS LOW
Data Valid after CS HIGH
LDAC LOW
RESET LOW
200
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
100
160
50
0
0
0
0
70
50
0
0
50
50
TABLE II. Timing Specifications (T
A
= –40
°
C to +85
°
C).
相關(guān)PDF資料
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