參數(shù)資料
型號(hào): DAC7724U
元件分類: 外設(shè)及接口
英文描述: Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C
中文描述: 電可擦除可編程邏輯器件
文件頁數(shù): 15/15頁
文件大?。?/td> 451K
代理商: DAC7724U
15
DAC7724, 7725
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
RCS
t
RDS
t
RDH
t
DZ
t
CSD
t
WCS
t
WS
t
WH
t
AS
t
AH
t
LD
t
DS
t
DH
t
LWD
t
RESET
t
S
CS LOW for Read
R/W HIGH to CS LOW
R/W HIGH after CS HIGH
CS HIGH to Data Bus in High Impedance
CS LOW to Data Bus Valid
CS LOW for Write
R/W LOW to CS LOW
R/W LOW after CS HIGH
Address Valid to CS LOW
Address Valid after CS HIGH
LDAC Delay from CS HIGH
Data Valid to CS LOW
Data Valid after CS HIGH
LDAC LOW
RESET LOW Time
Settling Time
200
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
100
100
160
50
0
0
0
0
10
0
0
50
50
10
TABLE II. Timing Specifications (T
A
= –40
°
C to +85
°
C).
FIGURE 4. Digital Input and Output Timing.
t
RCS
CS
t
RDS
t
RDH
t
AS
t
CSD
t
DZ
t
AH
R/W
A0/A1
Data Out
Data Valid
Data Read Timing
±
0.012% of FSR
Error Band
±
0.012% of FSR
Error Band
Mid-Scale
RESET
V
OUT
, DAC7725
+FS
–FS
V
OUT
, DAC7724
+FS
–FS
DAC7724/25 Reset Timing
t
RESET
t
S
t
WCS
CS
t
WS
t
AS
t
AH
t
WH
R/W
A0/A1
t
S
±
0.012% of FSR
Error Band
±
0.012% of FSR
Error Band
LDAC
t
DS
t
DH
Data In
V
OUT
Data Write Timing
t
LWD
t
LD
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