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| 型號(hào)： | DAC7731EB1K |
| 英文描述： | 16-Bit, Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 16位，電壓輸出，串行輸入數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 11/19頁(yè) |
| 文件大?。?/td> | 360K |
| 代理商： | DAC7731EB1K |
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DAC7731
SBAS249
11
www.ti.com
V
CC
REF
OUT
REF
IN
REFADJ
V
REF
R
OFFSET
AGND
RFB2
RFB1
SJ
V
OUT
V
DD
V
SS
REFEN
RSTSEL
SCLK
CS
SDO
SDI
LDAC
RST
NC
TEST
DGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DAC7731
1
μ
F
0.1
μ
F
V
CC
1
μ
F
0.1
μ
F
V
DD
Control/Data
Bus
1
μ
F
0.1
μ
F
V
SS
(
–
10V to +10V)
FIGURE 4. Basic Operation: V
OUT
=
–
10V to +10V.
ANALOG OUTPUTS
The output amplifier can swing to within 1.4V of the supply
rails, specified over the
–
40
°
C to +85
°
C temperature range.
This allows for a
±
10V DAC voltage output operation from
±
12V supplies with a typical 5% tolerance.
When the DAC7731 is configured for a unipolar, 0V to 10V
output, a negative voltage supply is required. This is due to
internal biasing of the output stage. Please refer to the
“
Electrical Characteristics
”
table for more information.
The minimum and maximum voltage output values are de-
pendent upon the output configuration implemented and
reference voltage applied to the DAC7731. Please note that
V
SS
(the negative power supply) must be in the range of
–
4.75V to
–
15.75V for unipolar operation. The voltage on V
SS
sets several bias points within the converter and is required
in all modes of operation. If V
SS
is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not ensured.
REFERENCE INPUTS
The DAC7731 provides a built-in +10V voltage reference and
on-chip buffer to allow external component reference drive. To
use the internal reference, REFEN must be LOW, enabling the
reference circuitry of the DAC7731 (as shown in Table I) and
the REF
OUT
pin must be connected to REF
IN
. This is the input
to the on-chip reference buffer. The buffer
’
s output is provided
at the V
REF
pin. In this configuration, V
REF
is used to setup the
DAC7731 output amplifier into one of three voltage output
modes as discussed earlier. V
REF
can also be used to drive
other system components requiring an external reference.
The internal reference of the DAC7731 can be disabled when
use of an external reference is desired. When using an
external reference, the reference input, REF
IN
, can be any
voltage between 4.75V (or V
SS
+ 14V, whichever is greater)
and V
CC
–
1.4V.
REFSEL
ACTION
1
Internal Reference disabled;
REF
OUT
= High Impedance
Internal Reference enabled;
REF
OUT
= +10V
0
TABLE I. REFEN Action.
DIGITAL INTERFACE
Table II shows the input data format for the DAC7731 and
Table III illustrates the basic control logic of the device. The
serial interface consists of a chip select input (CS), serial data
clock input (SCLK), serial data input (SDI), serial data output
(SDO), and load control input (LDAC). An asynchronous reset
input (RST), which is active LOW, is provided to simplify start-
up conditions, periodic resets, or emergency resets to a known
state, depending on the status of the reset select (RSTSEL)
signal. Please refer to the "DAC Reset" section for additional
information regarding the reset operation.
CONTROL STATUS
COMMAND
CS RST RSTSEL LDAC SCLK
H
H
X
ACTION
X
X
Shift Register is disabled on the serial bus.
Enable SDO pin from High Impedance;
enables shift operation and I/O bus
(SCLK, SDI, SDO).
Serial Data Shifted into Input Register
Serial Data Shifted into Input Register
(1)
Data in Input Register is Loaded into DAC Register.
Resets Input and DAC Registers to mid-scale.
Resets Input and DAC Registers to min-scale.
L
H
X
X
X
L
↑
X
X
X
NOTE: (1) In order to avoid unwanted shifting of the input register by an
additional bit, care must be taken that a rising edge on CS only occurs
when SCLK is HIGH.
H
H
H
L
L
X
X
X
H
L
X
X
↑
X
X
↑
L
X
X
X
TABLE III. DAC7731 Logic Truth Table.
ANALOG OUTPUT
TABLE II. DAC7731 Data Format.
DIGITAL INPUT
Unipolar Configuration
Bipolar Configuration
Unipolar Straight Binary
Zero (0V)
Zero + 1LSB
:
1/2 Full-Scale
1/2 Full-Scale + 1LSB
:
Full-Scale (V
REF
–
1LSB)
Bipolar Offset Binary
–
Full-Scale (
–
V
REF
or
–
V
REF
/2)
–
Full-Scale + 1LSB
:
Bipolar Zero
Bipolar Zero + 1LSB
:
+Full-Scale (+V
REF
–
1LSB
or +V
REF
/2
–
1LSB)
0x0000
0x0001
:
0x8000
0x8001
:
0xFFFF
The DAC code is provided via a 16-bit serial interface, as shown
in Table II. The digital input word makes up the digital code to
be loaded into the data input register of the device. A typical
data transfer and DAC output update takes place as follows:
Once CS is active (LOW), the DAC7731 is enabled on the serial
bus and the 16-bit serial data transfer can begin. The serial data
is shifted into the device on each rising SCLK edge until all 16
bits are transferred (1 bit per 1 rising SCLK edge). Once
received, the data in the input register is loaded into the DAC
register upon reception of a rising edge on the LDAC input (load
command). This action updates the analog output, V
OUT
, to the
desired voltage specified by the digital input word. A rising edge
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