參數(shù)資料
型號(hào)： DAC7731EB1K
英文描述： 16-Bit, Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
中文描述： 16位，電壓輸出，串行輸入數(shù)字到模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 4/19頁(yè)
文件大小： 360K
代理商： DAC7731EB1K
DAC7731
SBAS249
4
www.ti.com
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNITS
t
WH
t
WL
t
SDI
t
HDI
t
SCS
t
HSC
t
DDO
t
HDO
t
DDOZ
t
WCSH
t
WLDL
t
WLDH
SLD
t
DLD
SCLK HIGH Time
SCLK LOW Time
Setup Time: Data in valid before rising SCLK
Hold Time: Data in valid after rising SCLK
Setup Time: CS falling edge before first rising SCLK
Hold Time: CS rising edge after 16th rising SCLK
Delay Time: CS Falling Edge to Data Out valid, C
L
= 20pF on SDO
Hold Time: Data Out valid after SCLK rising edge, C
L
20pF on SDO
Delay Time: CS rising edge to SDO = High Impedance
CS HIGH Time
LDAC LOW Time
LDAC HIGH Time
Setup Time: 16th Rising SCLK Before LDAC Rising Edge
Delay Time: LDAC rising edge to first SCLK rising edge of next
transfer cycle.
Setup Time: CS High before falling SCLK edge following 16th
rising SCLK edge
Setup Time: RSTSEL Valid Before RST LOW
Hold Time: RSTSEL valid after RST HIGH
RST LOW Time
DAC V
OUT
Settling Time
25
25
5
20
15
0
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
50
20
20
15
15
t
SCLK
5
ns
t
SRS
t
HRS
t
WRL
S
0
20
30
ns
ns
ns
μ
s
5
TIMING CHARACTERISTICS
V
CC
= +15V, V
SS
=
–
15V, V
DD
= 5V; R
L
= 2k
to AGND; C
L
= 200pF to AGND; all specifications
–
40
°
C to +85
°
C, unless otherwise noted.
DAC7731
CS
SCLK
SDI
SDO
LDAC
V
OUT
t
SCS
t
HCS
t
WH
t
WL
t
SCLK
t
HDI
t
SDI
t
DDO
t
HDO
t
DDOZ
t
WLDL
t
DLD
t
SLD
t
S
t
WLDH
t
WCSH
1
2
16
B15
B14
B13
B0
A15
A14
A13
A0
C15
C14
C13
C12
B15
B14
B13
B12
Word B
Word A
Word C
Word B
±
0.003% of FSR
Error Bands
RSTSEL
(RSTSEL = LOW)
(RSTSEL = HIGH)
RST
V
OUT
V
OUT
t
SRS
t
HRS
t
WRL
t
S
+FS
+FS
–
FS
–
FS
Min-Scale
Mid-Scale
INTERFACE TIMING
RESET TIMING
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